NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 261

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.10.12
3.10.13
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
MSIAR: Message Signalled Interrupt Address Register
MSIDR: Message Signalled Interrupt Data Register
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:16
13:11
10:8
31:20
19:12
11:4
Bit
15
14
1:0
Bit
3
2
Attr
RW
RW
RW
RW
RV
Attr
RW
RW
RW
RW
RO
RV
8
0
5Ch
Intel 5000P Chipset
8
0
60h
Intel 5000P Chipset
Default
0000h
0h
Default
0h
0h
0h
FEEh
0h
0h
00
0
0
Reserved.
TM: Trigger Mode
This field Specifies the type of trigger operation
0: Edge
1: level
LVL: Level
if TM is 0h, then this field is a don’t care.
Edge triggered messages are consistently treated as assert messages.
For level triggered interrupts, this bit reflects the state of the interrupt input
if TM is 1h, then:
0: Deassert Messages
1: Assert Messages
These bits are don’t care in IOxAPIC interrupt message data field specification.
DM: Delivery Mode
000: Fixed
001: Lowest Priority
010: SMI/HMI
011: Reserved
100: NMI
101: INIT
110: Reserved
111: ExtINT
AMSB: Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address.
ADSTID: Address Destination ID
This field is initialized by software for routing the interrupts to the appropriate
destination.
AEXDSTID: Address Extended Destination ID
This field is not used by IA32 processor.
ARDHINT: Address Redirection Hint
0: directed
1: redirectable
ADM: Address Destination Mode
0: physical
1: logical
Reserved.
Not used since the memory write is D-word aligned
Description
Description
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