NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 377

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Table 5-26. Hot-Plug Signals on a Virtual Pin Port
5.16
5.16.1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
The Intel 5000P Chipset MCH will send Assert_intx/Deassert_intx or Assert_HPGPE/
Deassert_HPGPE messages to the ESI port as virtual pin messages to enable the Intel
631xESB/632xESB I/O Controller Hub take the appropriate action for handling the hot-
plug (legacy/ACPI interrupt mode) in non-MSI mode.
Clocking
The following section describes the Intel 5000P Chipset MCH Clocks.
Reference Clocks
The BUSCLK, and CORECLK (herein referred to “in aggregate” as “BUSCLK”) reference
clocks, operating at 133/166/266 MHz, are supplied to the Intel 5000P Chipset MCH.
These are the processor bus, core, and snoop filter PLL reference clocks. This frequency
is common between all processor bus agents. Phase matching between agents is
required. The two processor FSBs operate in phase with the core clock.
The FB-DIMM(0/1)CLK reference clocks, (herein referred to as FBDCLK) operating at
half the DDR2 frequency (operating at the SDRAM command-clock frequency, which is
the FB-DIMM packet frequency), are supplied to the Intel 5000P Chipset MCH. This is
the FB-DIMM PLL reference clock. This frequency is common between the Intel 5000P
Chipset MCH and DIMMs. Phase matching between agents is not required
(plesiochronous). The Intel 5000P Chipset MCH and DIMMs treat this frequency domain
synchronously. The FB-DIMM unit-interval (UI) PLL outputs 12x the FBDCLK frequency.
For example, for DDR2 667 MHz DIMMs, the FBDCLK frequency is 333 MHz and the UI
(link) frequency is 4.0 GHz.
The PECLK reference clock, operating at 100 MHz, is supplied to the Intel 5000P
Chipset MCH. This is the PCI Express PLL reference clock. The PCI Express flit PLL
outputs 250 MHz. The PCI Express phit PLL outputs 2.5 GHz. The phit clock frequency
must be tightly matched (mesochronous mode) between both PCI Express agents when
spectrum-spreading is not employed. The phit clock frequency is common to both PCI
Express agents when spectrum-spreading is employed. When the phit clock frequency
Bit
0
1
3
4
5
6
7
2
Direction
Output
Output
Output
Input
Input
Input
Input
Input
Voltage Logic
High_true
High_true
high_true
Low_true
Low_true
low_true
low_true
low_true
Level
BUTTON#
PWRFLT#
PWRLED
PRSNT#
ATNLED
PWREN
Signal
MRL#
GPI#
PWR Fault in the
VRM
Card Present in
Slot
Power is to be
enabled on the
Slot
MRL is open
Power good on
Slot
ATTN Button is
ATTN LED is to
PWR LED is to
be turned ON
be turned ON
Logic True
Meaning
Pressed
No PWR Fault in the VRM
Card NOT Present in Slot
Power is NOT to be
enabled on the Slot
MRL is closed
No Power good on Slot
Logic False Meaning
ATTN Button is NOT
ATTN LED is to be
PWR LED is to be
turned OFF
turned OFF
Pressed
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