NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 242

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.9.25.5
3.9.25.6
3.9.25.7
3.9.25.8
242
FBD[3:2]IBPATBUF: FB-DIMM IBIST Pattern Buffer Register
This register contains the pattern bits used in IBIST operations.
FBD[1:0]IBPATBUF: FB-DIMM IBIST Pattern Buffer Register
This register contains the pattern bits used in IBIST operations.
FBD[3:2]IBTXMSK: IBIST Transmitter Mask
This register determines which lanes are enabled for IBIST operations. These bits also
control the power saving features of each lane. If a particular lane is masked off, the
power to that lane is reduced as much as possible.
FBD[1:0]IBTXMSK: IBIST Transmitter Mask
This register determines which lanes are enabled for IBIST operations. These bits also
control the power saving features of each lane. If a particular lane is masked off, the
power to that lane is reduced as much as possible.
Device:
Function: 0
Offset:
31:24
23:0
Device:
Function: 0
Offset:
31:24
23:0
Device:
Function: 0
Offset:
31:14
13:10
9:0
Bit
Bit
Bit
RV
RWST
RV
RWST
RWST
RWST
Attr
Attr
Attr
RV
22
288h, 188h
21
288h, 188h
22
28Ch, 18Ch
0
02CCFDh
0
02CCFDh
Default
Default
Default
3FFh
0h
0h
Reserved
txmaskhvm: Transmit Mask extra DFT pins for HVM symmetry
Selects which lanes to enable for testing. A lane that is not selected remains
in electrical idle.
txmask: Transmit Mask
Selects which lanes to enable for testing. A lane that is not selected remains
in electrical idle.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Reserved
IBPATBUF: IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
Default: 0000_0010_1100_1100_1111_1101
Reserved
IBPATBUF: IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
Default: 0000_0010_1100_1100_1111_1101
Description
Description
Description
Register Description