NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 136

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.10.4
3.8.10.5
136
MSIAR[7:2, 0] - MSI Address Register
The MSI Address Register (MSIAR) contains the system specific address information to
route MSI interrupts and is broken into its constituent fields.
MSIDR[7:2, 0] - MSI Data Register
The MSI Data Register (MSIDR) contains all the data (interrupt vector) related
information to route MSI interrupts.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:20
19:12
31:16
11:4
1:0
Bit
Bit
3
2
Attr
Attr
RW
RW
RW
RW
RO
RV
RV
0, 2-3
0
5Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
5Ch
Intel 5000Z Chipset
4-7
0
5Ch
Intel 5000P Chipset
0, 2-3
0
60h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
60h
Intel 5000Z Chipset
4-7
0
60h
Intel 5000P Chipset
Default
Default
0000h
FEEh
00h
00h
0h
0h
0h
AMSB: Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address.
ADSTID: Address Destination ID
This field is initialized by software for routing the interrupts to the appropriate
destination.
AEXDSTID: Address Extended Destination ID
This field is not used by IA32 processor.
ARDHINT: Address Redirection Hint
0: directed
1: redirectable
ADM: Address Destination Mode
0: physical
1: logical
Reserved.
Not used since the memory write is D-word aligned
Reserved.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description