NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 264

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.10.18
264
PEXDEVCTRL - Device Control Register
Device:
Function:
Offset:
Version:
2:0
Device:
Function:
Offset:
Version:
15
14:12
11
10
9
8
7:5
4
Bit
Bit
RO
RV
RO
RW
RO
RO
RO
RW
RO
Attr
Attr
8
0
70h
Intel 5000P Chipset
8
0
74h
Intel 5000P Chipset
000
0
000
1
0
0
0
000
0
Default
Default
MPLSS:
This field indicates the maximum payload size that the CB integrated device can
support.
000: 128B max payload size
others- Reserved
Reserved
MRRS:
Since the DMA Engine device does not issue read requests on a PCI Express
interface, this field is irrelevant.
ENNOSNP: Enable No Snoop
1: Setting this bit enables the DMA Engine device to issue requests with the No
Snoop attribute.
0: Clearing this bit behaves as a global disable when the corresponding capability is
enabled for source/destination snoop control in the DMA’s descriptor’s Desc_Control
field.
APPME: Auxiliary Power PM Enable
The DMA Engine device does not implement auxiliary power so setting this bit has
no effect.
PFEN: Phantom Functions Enable
The DMA Engine device does not implement phantom functions so setting this bit
has no effect.
ETFEN: Extended Tag Field Enable:
The DMA Engine device does not implement extended tags so setting this bit has no
effect.
MPS: Max_Payload_Size:
The DMA Engine device must not generate packets on any PCI Express interface
which exceeds the length allowed with this field.
000: 128B max payload size
001: 256B max payload size
010: 512B max payload size
011: 1024B max payload size
100: 2048B max payload size
101: 4096B max payload size
Note:
ENRORD: Enable Relaxed Ordering
No relaxed ordering is supported by Intel 5000P Chipset MCH. Hardwired to 0h.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Max_Read_Request_Size
This field has no impact internally to
maximum payload size of the TLPs that appear on the PCI Express port is
governed by the PEXDEVCTRL.MPS for that port defined in
Max_Payload_Size Supported
Hardwired to 0h
Hardwired to 0h
Hardwired to 0h
Description
Description
Intel 5000P Chipset MCH
Register Description
Table 3.8.11.4
and the