NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 343

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Note:
5.12.1
Figure 5-16. x4 PCI Express Bit Lane
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
There is no PCI Express port designated as Port 1.
The ESI port is the primary interface to the Intel 631xESB/632xESB I/O Controller Hub.
This interface can be paired with up to two of the PCI Express ports (Port 2 and Port 3)
to increase available bandwidth to the Intel 631xESB/632xESB I/O Controller Hub. The
Intel 5000P Chipset MCH supports four general purpose PCI Express ports. These ports
are combinable to form two high performance x8 ports.
The following sections describe the characteristics of each of these port classes in
detail.
Intel 5000P Chipset MCH PCI Express Port Overview
The Intel 5000P Chipset MCH utilizes general purpose PCI Express high speed ports to
achieve superior I/O performance. The MCH PCI Express ports are compliant with the
PCI Express Interface Specification, Rev 1.0a.
A PCI Express port is defined as a collection of bit lanes. Each bit lane consists of two
differential pairs in each direction (transmit and receive) as depicted in
The raw bit-rate per PCI Express bit lane is 2.5 Gbit/s. This results in a real bandwidth
per bit lane pair of 250 MB/s given the 8/10 encoding used to transmit data across this
interface. The result is a maximum theoretical realized bandwidth on a x4 PCI Express
port of 1 GB/s in each direction.
Each of the Intel 5000P Chipset MCH PCI Express port are organized as four bi-
directional bit lanes, and are referred to as a x4 port.
• Enterprise South Bridge Interface (ESI), Port 0
• General purpose ports, Port 2, Port 3, Port 4, Port 5, Port 6, and Port 7
O
P
R
T
Rx
Tx
Rx
Rx
Rx
Tx
Tx
Tx
AC coupling capacitors
AC coupling capacitors
AC coupling capacitors
AC coupling capacitors
LINK (x4)
LANE 3
LANE 1
LANE 2
LANE 0
Rx
Tx
Tx
Rx
Rx
Rx
Tx
Tx
O
T
P
R
Table
5-16.
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