NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 52

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table 3-3.
Table 3-4.
52
Functions Specially Handled by the MCH
To comply with the PCI specification, accesses to non-existent functions, registers, and
bits will be master aborted. This behavior is defined in the following table:
Access to “Non-Existent” Register Bits
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
DIMM
MCH
MCH
MCH
MCH
MCH
MCH
Devices listed in
ESI Device Identification” on page 51
functions not listed
Devices listed in
ESI Device Identification” on page 51,
registers not listed in
Definitions.”
Reserved bits in registers
Component
PCI Express Port 2
PCI Express Port 3
PCI Express Port 4
PCI Express Port 5
PCI Express Port 6
PCI Express Port 7
DMA Engine
DMA Engine MMIO Space
Memory Map, Error Flag/Mask,
RAS, Channel Control for FB-
DIMM Branch 0
Memory Map, Error Flag/Mask,
RAS, Channel Control for FB-
DIMM Branch 1
Processor Bus, Boot, Interrupt,
System Address
AMB Memory Mapped registers
Address Mapping, Memory
Control, Error Logs
FSB Error Registers
PCI Express Port 2-3
PCI Express Port 4-5
PCI Express Port 6-7
PCI Express Port 4-7
Table 3-2, “Memory Control Hub
Table 3-2, “Memory Control Hub
Access to
SSection 3.8, “Register
Register Group
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
but to
but to
25E2h
25E3h
25E4h
25E5h
25E6h
25E7h
1A38h
N/A
25F5h
25F6h
25F0h
N/A
25F0h
25F0h
25F7h
25F8h
25F9h
25FAh
Have no effect
Have no effect
Software must read-
modify-write to preserve
the value
DID
2
3
4
5
6
7
8
8
21
22
16
9
16
16
2
4
6
4
Writes
Device
0
0
0
0
0
0
0
1
0
0
0
0
1
2
0
0
0
0
Functio
n
MCH returns all zeroes
MCH returns all zeroes
MCH returns all ones
Depending on what is
connected to these
ports, some may not be
accessible.
New device mapping for
DMA Engine
Debug and DFT in
higher address offsets.
Debug and DFT in
higher address offsets.
Debug and DFT in
higher address offsets.
Route out to AMB per
AMBSELECT register
only for JTAG/SMBus.
Debug and DFT in
higher address offsets.
x8 mode. Only port 2 is
active
x8 mode. Only port 4 is
active
x8 mode. Only port 6 is
active
x16 mode. Only port 4
is active
Register Description
Comment
Reads