NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 104
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NQ5000P S L9TN
Manufacturer Part Number
NQ5000P S L9TN
Description
Manufacturer
Intel
Datasheet
1.NQ5000P_S_L9TN.pdf
(530 pages)
Specifications of NQ5000P S L9TN
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
- Current page: 104 of 530
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Figure 3-4.
3.8.8
104
PCI Express Configuration Space
Figure 3-3
Express ports as defined in the PCI-Express Base Specification, Revision 1.0a. It is also
compatible with the standard PCI 2.3 capability structure and comprises of a linked list
where each capability has a pointer to the next capability in the list. For PCI Express
extended capabilities, the first structure is required to start at 0x100 offset.
PCI Express Header
The following registers define the standard PCI 2.3 compatible and extended PCI
Express configuration space for each of the PCI Express x4 links in the MCH. Unless
otherwise specified, the registers are enumerated as a vector [2:7] mapping to each of
the six PCI Express ports uniquely while the ESI port is referred by index 0.
shows the configuration register offset addresses for each of the PCI
Chipset Advanced Error
PCI-Express Advanced
PCI-Express Capability
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Intel® 5000P
MSI Capability
PM Capability
Error Reporting
Reporting
P2P
CAP_PTR
0x100
0xFFF
0x140
0x40
0x00
Register Description
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