NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 365

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Figure 5-30. DWORD Memory Read Protocol (SMBus Block Write / Bock Read, PEC
Figure 5-31. DWORD Memory Write Protocol
Figure 5-32. DWORD Configuration Read Protocol (SMBus Word Write / Word Read,
Figure 5-33. DWORD Configuration Write Protocol (SMBus Word Write, PEC Disabled)
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Disabled)
PEC Disabled)
S
S
Sr
S
S
S
Sr
S
Sr
S
S
S
S
S
S
Sr
S
S
S
0110_000
0110_000
0110_000
S
A
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
0110_000
Data[23:16]
0110_000
W A
W A
R A
W A
Cmd = 11100010
Cmd = 11100010
Byte Count = 5
A
W A
W A
W A
W A
W A
W A
Cmd = 11101110
W A
W A
W A
W A
R A
R A
W A
R A
W A
W A
Data[16:8]
A
A
A
Cmd = 10001101
Cmd = 10101101
Cmd = 00001101
Cmd = 00001101
Cmd = 01001101
Cmd = 00101101
Cmd = 10000001
Cmd = 10000001
Cmd = 00000001
Cmd = 01000001
Cmd = 01000000
Cmd = 00101101
Cmd = 01101101
A
A
Byte Count = 4
Data[23:16]
Status
Data[7:0]
Status
Byte Count = 8
Data[7:0]
A
A
A
CLOCK STRETCH
Destination Mem
A
A
A
A
A
A
Data[31:24]
A
A
A
A
A
A
N
A
A
A
Destination Mem
P
Register Num[15:8]
Register Num[15:8]
Add Offset[15:8]
A P
Bus Number
Data[31:24]
Dest Mem
Bus Number
Data[15:8]
Data[31:24]
Data[31:24]
Data[15:8]
Data[15:8]
A
A
A
Add Offset[23:16]
Add Offset[23:16]
Data[23:16]
A
A
A
A
A
A
A
A
A
A
N
N
A
A
A
P
P
Add Offset[15:8]
Add Offset[15:8]
Device/Function
Add Offset[23:16]
Register Num[7:0]
Data[15:8]
Device/Function
Add Offset[7:0]
Register Num[7:0]
Data[23:16]
Data[7:0]
Data[23:16]
Data[7:0]
A
A
A
Add Ofset[7:0]
Add Offset[7:0]
Data[7:0]
A P
A P
A P
A P
A P
CLOCK STRETCH
A P
CLOCK STRETCH
A P
CLOCK STRETCH
A
N P
CLOCK STRETCH
Data[31:24]
A P
A P
A P
A P
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