NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 149

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.11.8
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
PEXLNKSTS[7:2, 0] - PCI Express Link Status Register
The PCI Express Link Status register provides information on the status of the PCI
Express Link such as negotiated width, training, and so forth.
a. The NLNKWD field is set to a default value corresponding to x4 internally within the Intel 5000P Chipset MCH.
Notes:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:13
9:4
3:0
Note that this field is a don’t care until training is completed for the link. Software should not use this field to
determine whether a link is up (enabled) or not.
Bit
12
11
10
RWO
Attr
RO
RO
RO
RO
RV
0, 2-3
0
7Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
7Eh
Intel 5000Z Chipset
4-7
0
7Eh
Intel 5000P Chipset
Default
000100
0h
1h
1
0
0
Reserved.
SCCON: Slot Clock Configuration
This bit indicates that the component uses the same physical reference clock
that the platform provides on the connector. If the device uses an independent
clock irrespective of the presence of a reference on the connector, this bit
must be clear.
1:
platform.
0: indicates independent clock on the PCI Express connector from that of the
platform.
The Intel 5000P Chipset MCH initializes this bit to '1' because the expected
state of the platform is to have one clock source shared between the Intel
5000P Chipset MCH component and any down-devices or slot connectors. It is
the responsibility of BIOS to be aware of the real platform configuration, and
clear this bit if the reference clocks differ.
LNKTRG: Link Training
This field indicates the status of an ongoing link training session in the current
PCI Express port and is controlled by the Hardware.
0: indicates that the LTSSM is neither in “Configuration” nor “Recovery” states.
1: indicates Link training in progress (Physical Layer LTSSM is in
Configuration or Recovery state or the RLNK (retrain link) was set in
Section 3.8.11.7
Also refer to the BCTRL.SBUSRESET for details on how the Link training bit can
be used for sensing Hot-reset states.
TERR: Training Error
This field indicates the occurrence of a Link training error.
0: indicates no Link training error occurred.
1: indicates Link training error occurred.
NLNKWD: Negotiated Link Width
This field indicates the negotiated width of the given PCI Express link after
training is completed.
Only x1, x4, x8, and x16 link width negotiations are possible in the Intel
5000P Chipset MCH. Refer to
assignment after training is completed.
LNKSPD: Link Speed
This field indicates the negotiated Link speed of the given PCI Express Link:
0001- 2.5 Gb/s PCI Express link
Others -
indicates same physical clock in the PCI Express connector as in the
Reserved
but training has not yet begun.
Table 3-36
Description
a
for the port and link width
149