NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 124

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

124
Device:
Function: 0
Offset:
3:1
0
Bit
RWST
RWST
Attr
0
40h
000
0
Default
GPMNXT0: IOU0 max width Configuration Next (ports 2-3)
The IOU0 cluster will use this field to train the links after a hard reset provided
LWOEN is set.
Refer to
page 126
LWOEN: Link Width override Enable
0: Disables software from setting the PCI Express link width through this register
and the Link width is controlled by the external pins PEWIDTH[3:0]. (default).
1. Enables BIOS/Software to set the required link width through this register. When
this bit is set, the IOU cluster will ignore the external pin strap (PEWIDTH[3:0] and
use the described table for configuring the link width. The values will take effect
after a hard reset.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Table 3.8.8.30, “PEXCTRL[7,2:0]: PCI EXPRESS Control Register” on
Description
Register Description