NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 189

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.13.20
3.8.13.21
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
NRECINT - Non Recoverable Internal MCH Error Log Register
This register will log non-recoverable errors (Fatal and Non Fatal) based on the internal
MCH errors that originate from the FERR_FAT_INT, FERR_NF_INT described starting
from
VPP_PEX_PORT2-3 is set, then software can scan the PCI Express configuration space
for unit errors logged in the device 2,3 for PEX_UNIT_FERR/NERR register as defined in
Section 3.8.12.28
FB-DIMM Channels when VPP_FBD is set.
RECINT - Recoverable Internal MCH Data Log Register
This register is not currently used as there are no correctable errors with in the internal
data path of the MCH.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:21
20:13
12:11
31:21
20:13
12:11
10:8
6:0
Bit
Bit
Bit
1
0
7
Section
RWCST
RWCST
ROST
ROST
ROST
ROST
Attr
Attr
Attr
RV
RV
RV
RV
RV
16
2
C3h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
2
C4h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
2
C8h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
3.8.13.16. For debugging VPP errors in this register, for example, if
Default
Default
00000
to determine the failing port. The same can be repeated for the
Default
0h
0h
00
0h
0h
0h
00
0
0
0
Reserved
DM entry
Reserved
Internal Block that detected the Failure
001: VPP_PEX_PORT2-3
010: VPP_PEX_PORT4-7
011: VPP_FBD
100: COH
101: DM
Others: Reserved
Reserved
COH Entry of Failed Location
Reserved
DM entry
Reserved
B6Err: Single ECC error on SF lookup (SF)
B5Err: Address Map Error (COH)
Description
Description
Description
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