NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 318

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5.2.12.3
5.2.12.4
5.2.12.5
318
1.
2. GBLTHRT* is an internal combinatorial signal before it is latched in the THRSTS.GBLTHRT register
Intel 5000P Chipset
recommendation for CKE low to high transition.
field to enable the open loop throttling logic to use the latest value of the signal.
CKE State Near End of Activation Throttling Window
If the throttling begins very close to the end of the window, then the assertion of CKE
low command would be delayed beyond the end of the throttle window. To prevent this
occurrence, the memory controller logic does not observe a throttle event in the last
few clocks of the window, or assert a CKE low command.
If the activation throttle is set to begin within Y clocks before the end of the window,
the memory controller skips the asserting CKE low step, where Y is X + 6
number “6” is derived from 3 clocks for the CKE low to high minimum, plus another 3
clocks for the CKE high until first command after the throttling window.
Refresh Handling During Throttling
The Intel 5000P Chipset memory controller ensures that refreshes, which are lost
during the activation throttle period (possibly up to 2), are made up at the end of the
period. Double refresh rates to the DIMMs should be carried out when needed
regardless of the setting of the MC.THRMHUNT bit. This is particularly important for
open loop throttling when the temperature could rise beyond 85’C.
Throttling Parameters for Activation Throttling.
The current throttling parameters for each branch are stored in the THRMTHRT register
field defined in
registers are 8-bits wide, and provide increments of 4 activations per throttle window
(1344 clocks). Three levels of throttling limits are defined.
The MC.THRMHUNT bit must be enabled for the temperature to have any influence on
the throttle parameters. If MC.THRMHUNT=0, only the GBLTHRT bit from the Global
Throttle Window, when enabled can change the THRMTHRT register field. Refer to
Figure 5-10
• THRTLOW: A base throttling level that is applied when the temperature is in the low
• THRTMID: A mid level throttling level that is applied when the temperature is in the
• THRTHI: The highest level of throttling. When MC.THRMODE=1, this level is applied
range (below T
Throttling Window logic. See
middle range (above T
Global Throttling Window logic. See
whenever the temperature is above T
ceiling of the hunting algorithm of the closed loop throttling. The temperature being
above T
throttling level takes precedence). See
mid
and
MC design needs to adjust the value based on the latest JEDEC
Section
has priority over the Global Throttling Window throttling (the higher
Figure 5-11
low
) and the THRTSTS.GBLTHRT*
3.9.3. All activation throttling parameters in the THRMTHRT
low
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
for the thermal envelopes.
but below T
Section 3.9.4
Section 3.9.5
mid
mid
Section 3.9.6
) or the THRSTS.GBLTHRT* bit is set by the
. When MC.THRMODE=0, this level is the
2
bit is not set by the Global
Functional Description
1
(and the