NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 186

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.13.12
.
3.8.13.13
3.8.13.14
186
ERR2_FSB[1:0]: FSB Error 2 Mask Register
This register enables the signaling of Err[2] when an error flag is set. Note that one and
only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
ERR1_FSB[1:0]: FSB Error 1 Mask Register
This register enables the signaling of Err[1] when an error flag is set. Note that one and
only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
ERR0_FSB[1:0]: FSB Error 0 Mask Register
This register enables the signaling of Err[0] when an error flag is set. Note that one and
only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:9
15:9
Bit
Bit
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
Attr
Attr
RV
RV
RV
RV
RV
RV
RV
RV
16
0
498h, 198h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
0
496h, 196h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
Default
0h
0h
0h
0h
0h
0h
0h
1
1
1
1
1
1
1
1
1
1
0
1
1
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Reserved
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
Reserved
Reserved
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
Reserved
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
Reserved
Reserved
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
Description
Description
Register Description