Z8F08200100KIT Zilog, Z8F08200100KIT Datasheet - Page 108

• Manufacturer Part Number: Z8F08200100KIT
• Description: DEV KIT FOR Z8 ENCORE 4K TO 8K
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F08200100KIT

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Data Bus Width: 8 bit
• Interface Type: RS-485
• Silicon Manufacturer: Zilog
• Core Architecture: Z8 Encore
• Silicon Core Number: Z8F0822SJ020
• Silicon Family Name: XP F0822
• For Use With/related Products: Z8 Encore!™
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3183

PS022517-0508
1
0
Idle State
of Line
Clear To Send Operation
Multiprocessor (9-bit) Mode
Start
The CTS pin, if enabled by the
flow control on the outgoing transmit datastream. The Clear To Send (CTS) input pin is
sampled one system clock before beginning any new character transmission. To delay
transmission of the next data character, an external receiver must deassert CTS
at least one system clock cycle before a new data transmission begins. For multiple
character transmissions, this would be done during
deasserts in the middle of a character transmission, the current character is sent
completely.
The UART has a MULTIPROCESSOR (9-bit) mode that uses an extra (9th) bit for
selective communication when a number of processors share a common UART bus.
In MULTIPROCESSOR mode (also referred to as 9-bit mode), the multiprocessor bit is
transmitted following the 8-bits of data and immediately preceding the
played in
In MULTIPROCESSOR (9-bit) mode, the Parity bit location (9th bit) becomes the
Multiprocessor control bit. The UART Control 1 and Status 1 Registers provide
Multiprocessor (9-bit) mode control and status information. If an automatic address
matching scheme is enabled, the UART Address Compare Register holds the network
address of the device.
MULTIPROCESSOR (9-bit) Mode Receive Interrupts
When multiprocessor mode is enabled, the UART only processes frames addressed to it.
The determination of whether a frame of data is addressed to the UART can be made in
hardware, software, or combination of the two depending on the multiprocessor configura-
tion bits. In general, the address compare feature reduces the load on the CPU, because it
does not need to access the UART when it receives data directed to other devices on the
Figure 14. UART Asynchronous MULTIPROCESSOR Mode Data Format
Bit0
lsb
Figure
Bit1
14. The character format is as displayed in
Bit2
Bit3
Data Field
CTSE
Bit4
bit of the UART Control 0 register, performs
Bit5
Universal Asynchronous Receiver/Transmitter
STOP
Bit6
Z8 Encore! XP
bit transmission. If CTS
msb
Bit7
Figure
Product Specification
MP
14.
STOP
®
1
F0822 Series
STOP Bit(s)
bit(s) as dis-
2
95