Z8F08200100KIT Zilog, Z8F08200100KIT Datasheet - Page 110

• Manufacturer Part Number: Z8F08200100KIT
• Description: DEV KIT FOR Z8 ENCORE 4K TO 8K
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F08200100KIT

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Data Bus Width: 8 bit
• Interface Type: RS-485
• Silicon Manufacturer: Zilog
• Core Architecture: Z8 Encore
• Silicon Core Number: Z8F0822SJ020
• Silicon Family Name: XP F0822
• For Use With/related Products: Z8 Encore!™
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3183

PS022517-0508
DE
1
0
1
0
Idle State
of Line
UART Interrupts
Enable signal asserts at least one UART bit period and no greater than two UART bit peri-
ods before the Start bit is transmitted. This format allows a setup time to enable the trans-
ceiver. The Driver Enable signal deasserts one system clock period after the last STOP bit
is transmitted. This one system clock delay allows both time for data to clear the trans-
ceiver before disabling it, as well as the ability to determine if another character follows
the current character. In the event of back to back characters (new data must be written to
the Transmit Data Register before the previous character is completely transmitted) the
DE signal is not deasserted between characters. The DEPOL bit in the UART Control
Register 1 sets the polarity of the Driver Enable signal.
The Driver Enable to Start bit setup time is calculated as follows:
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the BRG also functions as a basic timer
with interrupt capability.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(
transmission. The TDRE interrupt occurs after the Transmit shift register has shifted the
first bit of data out. At this point, the Transmit Data Register can be written with the next
character to send. This provides 7 bit periods of latency to load the Transmit Data Register
before the Transmit shift register completes shifting the current character. Writing to the
UART Transmit Data Register clears the
Start
TDRE
Figure 15. UART Driver Enable Signal Timing (with 1 STOP Bit and Parity)
⎛
⎝
---------------------------------------- -
Baud Rate (Hz)
) is set to 1. This indicates that the transmitter is ready to accept new data for
Bit0
lsb
1
Bit1
⎞
⎠
≤
Bit2
DE to Start Bit Setup Time (s)
Bit3
Data Field
Bit4
TDRE
Bit5
bit to 0.
Universal Asynchronous Receiver/Transmitter
Bit6
Z8 Encore! XP
≤
⎛
⎝
---------------------------------------- -
Baud Rate (Hz)
msb
Bit7
Product Specification
2
Parity
®
STOP Bit
F0822 Series
⎞
⎠
1
97