Z8F08200100KIT Zilog, Z8F08200100KIT Datasheet - Page 161

• Manufacturer Part Number: Z8F08200100KIT
• Description: DEV KIT FOR Z8 ENCORE 4K TO 8K
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F08200100KIT

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Data Bus Width: 8 bit
• Interface Type: RS-485
• Silicon Manufacturer: Zilog
• Core Architecture: Z8 Encore
• Silicon Core Number: Z8F0822SJ020
• Silicon Family Name: XP F0822
• For Use With/related Products: Z8 Encore!™
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3183

Operation
PS022517-0508
Automatic Power-Down
Single-Shot Conversion
Continuous Conversion
If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles,
portions of the ADC are automatically powered-down. From this power-down state, the
ADC requires 40 system clock cycles to power-up. The ADC powers up when a
conversion is requested using the ADC Control Register.
When configured for single-shot conversion, the ADC performs a single analog-to-digital
conversion on the selected analog input channel. After completion of the conversion, the
ADC shuts down. Follow the steps below for setting up the ADC and initiating a single-
shot conversion:
1. Enable the desired analog inputs by configuring the GPIO pins for alternate function.
2. Write to the ADC Control Register to configure the ADC and begin the conversion.
3. CEN remains 1 while the conversion is in progress. A single-shot conversion requires
4. When the conversion is complete, the ADC control logic performs the following
5. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
When configured for continuous conversion, the ADC continuously performs an
analog-to-digital conversion on the selected analog input. Each new data value over-writes
the previous value stored in the ADC Data Registers. An interrupt is generated after each
conversion.
This configuration disables the digital input and output drivers.
The bit fields in the ADC Control Register is written simultaneously:
–
–
–
–
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered-down state, the ADC uses 40 additional clock cycles to power-up
before beginning the 5129 cycle conversion.
operations:
–
–
–
powered-down.
Write to the ANAIN[3:0] field to select one of the 5 analog input sources.
Clear CONT to 0 to select a single-shot conversion.
Write to the VREF bit to enable or disable the internal voltage reference generator.
Set CEN to 1 to start the conversion.
10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]}.
CEN resets to 0 to indicate the conversion is complete.
An interrupt request is sent to the Interrupt Controller.
Z8 Encore! XP
Product Specification
Analog-to-Digital Converter
®
F0822 Series
148