Z8F08200100KIT Zilog, Z8F08200100KIT Datasheet - Page 144

• Manufacturer Part Number: Z8F08200100KIT
• Description: DEV KIT FOR Z8 ENCORE 4K TO 8K
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F08200100KIT

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Data Bus Width: 8 bit
• Interface Type: RS-485
• Silicon Manufacturer: Zilog
• Core Architecture: Z8 Encore
• Silicon Core Number: Z8F0822SJ020
• Silicon Family Name: XP F0822
• For Use With/related Products: Z8 Encore!™
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3183

PS022517-0508
Address Only Transaction with a 7-bit Address
When reading data from the slave, the I
the receive interrupt is serviced and the
the I
data byte.
In the situation where software determines if a slave with a 7-bit address is responding
without sending or receiving data, a transaction can be done which only consists of an
address phase.
if a slave with a 7-bit address will acknowledge. As an example, this transaction can be
used after a “write” has been done to a EEPROM to determine when the EEPROM com-
pletes its internal write operation and is once again responding to I
slave does not Acknowledge, the transaction is repeated until the slave does Acknowl-
edge.
Follow the steps below for an address only transaction to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE bit by writing a 7-bit Slave address plus write bit (=0)
5. Software sets the START and STOP bits of the I
6. The I
7. The I
8. Software polls the STOP bit of the I
9.
to the I
write operation.
TXI bit.
Register.
STOP bit when the address only transaction is completed.
the ACK bit is equal to 1. If the slave does not acknowledge, the ACK bit is equal to 0.
The NCKI interrupt does not occur in the not acknowledge case because the STOP bit
was set.
2
Software checks the ACK bit of the I
C Data Register. Once the I
2
2
2
Figure 26. 7-Bit Address Only Transaction Format
C interrupt asserts, because the I
C Controller sends the START condition to the I
C Controller loads the I
2
C Data Register. As an alternative this could be a read operation instead of a
Figure 26
S
Slave Address
on page 131 displays this “address only” transaction to determine
2
C Data Register has been read, the I
2
C Shift register with the contents of the I
W = 0 A/A
RDRF
2
2
2
2
C pauses after the data Acknowledge cycle until
C Control Register. Hardware deasserts the
C Control Register.
C Control Register to enable Transmit interrupts.
2
2
C Status Register. If the slave acknowledged,
C Data Register is empty (TDRE = 1)
bit of the status register is cleared by reading
2
C Control Register and clears the
P
Z8 Encore! XP
2
C Slave.
Product Specification
2
C transactions. If the
2
C reads the next
®
F0822 Series
2
C Data
I2C Controller
131