Z8F08200100KIT Zilog, Z8F08200100KIT Datasheet - Page 129

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Z8F08200100KIT

Manufacturer Part Number
Z8F08200100KIT
Description
DEV KIT FOR Z8 ENCORE 4K TO 8K
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Datasheets

Specifications of Z8F08200100KIT

Contents
Evaluation Board, Cable, Power Supply, Software and Documentation
Data Bus Width
8 bit
Interface Type
RS-485
Silicon Manufacturer
Zilog
Core Architecture
Z8 Encore
Silicon Core Number
Z8F0822SJ020
Silicon Family Name
XP F0822
For Use With/related Products
Z8 Encore!™
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3183
PS022517-0508
SPI Clock Phase and Polarity Control
The Master and Slave are each capable of exchanging a character of data during a
sequence of NUMBITS clock cycles (see NUMBITS field in the SPIMODE Register). In
both Master and Slave SPI devices, data is shifted on one edge of the SCK and is sampled
on the opposite edge where data is stable. Edge polarity is determined by the SPI phase
and polarity control.
Slave Select
The active Low Slave Select (SS) input signal selects a Slave SPI device. SS must be Low
prior to all data communication to and from the Slave device. SS must stay Low for the
full duration of each character transferred. The SS signal can stay Low during the transfer
of multiple characters or can deassert between each character.
When the SPI is configured as the only Master in an SPI system, the SS pin is set as either
an input or an output. For communication between the Z8 Encore! XP F0822 Series
device’s SPI Master and external Slave devices, the SS signal, as an output, asserts the SS
input pin on one of the Slave devices. Other GPIO output pins can also be employed to
select external SPI Slave devices.
When the SPI is configured as one Master in a multi-master SPI system, the SS pin should
be set as an input. The SS input signal on the Master must be High. If the SS signal goes
Low (indicating another Master is driving the SPI bus), a Collision error flag is set in the
SPI Status Register.
The SPI supports four combinations of serial clock phase and polarity using two bits in the
SPI Control Register. The clock polarity bit, CLKPOL, selects an active high or active low
clock and has no effect on the transfer format. Table 62 lists the SPI Clock Phase and
Polarity Operation parameters. The clock phase bit, PHASE, selects one of two fundamen-
tally different transfer formats. For proper data transmission, the clock phase and polarity
must be identical for the SPI Master and the SPI Slave. The Master always places data on
the MOSI line a half-cycle before the receive clock edge (SCK signal), in order for the
Slave to latch the data.
Table 62. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation
PHASE
0
0
1
1
CLKPOL
0
1
0
1
SCK Transmit
Edge
Falling
Rising
Rising
Falling
SCK Receive
Edge
Rising
Falling
Falling
Rising
Z8 Encore! XP
Product Specification
SCK Idle
State
Low
High
Low
High
Serial Peripheral Interface
®
F0822 Series
116

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