Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 89
Z8FMC04100
Manufacturer Part Number
Z8FMC04100
Description
Z8 Encore-R Motor Control Flash MCUs
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.Z8FMC04100.pdf
(402 pages)
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Pulse-Width Modulator
PS024604-1005
Architecture
The Z8FMC16100 Series Flash MCU includes a Pulse-Width Modulator (PWM) opti-
mized for Motor Control applications. The PWM features include:
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The PWM unit consists of a master timer to generate the modulator time base and six inde-
pendent compare registers to set the pulse-width modulation for each output. The six out-
puts are designed to provide control signals for inverter drive circuits. As such, the outputs
are grouped into pairs consisting of a High driver and a Low driver output. The output
pairs are programmable to operate independently or as complementary signals. In comple-
mentary output mode, a programmable dead time is inserted to ensure nonoverlapping sig-
nal transitions. The master count and compare values feed into modulator logic that
generates the proper transitions in the output states. Output polarity and fault/OFF state
control logic allows programming of the default OFF states, which forces the outputs to a
safe state in the event a fault in the motor drive is detected.
Figure 7 illustrates the architecture of the PWM modulator.
6 independent PWM outputs or 3 complementary PWM output pairs
Programmable deadband insertion for complementary output pairs
Edge-aligned or center-aligned PWM signal generation
PWM OFF state is option-bit-programmable
PWM outputs driven to OFF state on System Reset
Asynchronous disabling of PWM outputs on system fault; outputs are forced to OFF
state
FAULT inputs generate pulse-by-pulse or hard shutdown
12-bit reload counter with 1-, 2-, 4-, or 8-bit programmable clock prescaler
High current source and sink on all PWM outputs
PWM pairs can be used as general-purpose inputs when outputs are disabled
Analog-to-digital converter synchronized with PWM period
Narrow pulse suppression with programmable threshold
P R E L I M I N A R Y
Product Specification
Architecture
67
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