Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 276

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

254
Z8 Encore!
Product Specification
On-Chip Debugger
RESET
FIELD
BITS
R/W
OCD Status Register
®
Motor Control Flash MCUs
IDLE
BRKPC—Break when PC == OCDCNTR
If this bit is set to 1, then the OCDCNTR register is used as a hardware breakpoint. When
the program counter matches the value in the OCDCNTR register, DBGMODE is auto-
matically set to 1. If this bit is set, the OCDCNTR register does not count when the CPU is
running.
0 = OCDCNTR is setup as counter
1 = OCDCNTR generates hardware break when PC == OCDCNTR
BRKZRO—Break when OCDCNTR ==
If this bit is set, then the OCD automatically sets the DBGMODE bit when the OCD-
CNTR register counts down to
when the part leaves DEBUG Mode.
0 = OCD does not generate BRK when OCDCNTR decrements to
1 = OCD sets DBGMODE to 1 when OCDCNTR decrements to
Reserved—Must be 0.
RST—Reset
Setting this bit to 1 resets the device. The controller goes through a normal Power-On
Reset sequence with the exception that the On-Chip Debugger is not reset. This bit is auto-
matically cleared to 0 when the reset finishes.
0 = No effect.
1 = Reset the device.
The OCD Status Register, shown in Table 136, reports status information about the current
state of the debugger and the system. A more detailed description of each bit follows the
table.
Table 136. OCD Status Register (OCDSTAT)
IDLE—CPU idle
This bit is set if the part is in Debug mode (DBGMODE is 1) or if a BRK instruction has
occurred since the last time OCDCTL was written. This can be used to determine if the
CPU is running or if it is idle.
0 = The eZ8 CPU is running.
1 = The eZ8 CPU is either stopped or looping on a BRK instruction.
R
7
0
HALT
R
6
0
RPEN
R
5
0
P R E L I M I N A R Y
0000H
4
. If this bit is set, the OCDCNTR register is not reset
0000H
3
Reserved
R
2
0
0000H
0000H
1
PS024604-1005
0