Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 202

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

180
Z8 Encore!
Product Specification
s
I2C Master/Slave Controller
S
Slave Address
Figure 33. Data Transfer Format—Slave Receive Transaction with 10-Bit Address
1st Byte
®
Motor Control Flash MCUs
Slave Receive Transaction with 10-Bit Address
The data transfer format for writing data from a master to a slave with 10-bit addressing is
shown in Figure 33. The procedure that follows describes the I
operating as a slave in 10-bit addressing mode and receiving data from the bus master.
1. The software configures the controller for operation as a slave in 10-bit addressing
2. The master initiates a transfer, sending the first address byte. The I
3. The master sends the second address byte. The SLAVE mode I
4. The software responds to the interrupt by reading the I2CISTAT Register, which clears
5. The master detects the Acknowledge and sends the first byte of data.
6. The I
mode, as follows.
a. Initialize the
b. Optionally set the
c. Initialize the
d. Set
nizes the start of a 10-bit address with a match to
0 (a Write from the master to the slave). The I
it is available to accept the transaction.
address match between the second address byte and
I2CISTAT Register is set to 1, thereby causing an interrupt. The
indicating a Write to the slave. The I
able to accept the data.
the
first byte of data is received. If the software is only able to accept a single byte, it sets
the
Acknowledge, depending on the state of the
controller generates the receive data interrupt by setting the
Register.
SAM
NAK
mode or MASTER/SLAVE mode with 10-bit addressing.
the I2CMODE Register.
2
W=0
C controller receives the first byte and responds with Acknowledge or Not
IEN
bit. Because
bit in the I2CCTL Register.
= 1 in the I2CCTL Register. Set
A
SLA[7:0]
MODE
Slave Address
RD
GCE
field in the I2CMODE Register for either SLAVE ONLY
2nd Byte
P R E L I M I N A R Y
= 0, no immediate action is taken by the software until the
bit.
bits in the I2CSLVAD Register and the
2
C controller acknowledges, indicating it is avail-
A
NAK
NAK
Data
2
C controller acknowledges, indicating
SLA[9:8]
bit in the I2CCTL Register. The I
= 0 in the I
SLA[7:0]
A
2
C Master/Slave Controller
RDRF
and detects the R/W bit =
2
Data
C Control Register.
2
C controller detects an
. The
RD
bit in the I2CISTAT
2
C controller recog-
bit is cleared to 0,
SLA[9:8]
SAM
A/A
PS024604-1005
bit in the
P/S
bits in
2
C