Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 150

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

128
Z8 Encore!
Product Specification
LIN-UART
System
Clock
Architecture
Operation
LIN-UART
®
Motor Control Flash MCUs
•
•
•
Figure 17 illustrates how the noise filter is integrated with the LIN-UART for use on a
LIN network.
The figure below illustrates the operation of the noise filter both with and without noise.
The noise filter in this example is a 2-bit up/down counter which saturates at
11b.
The output of the filter switches from 1 to 0 when the counter counts down from
00b
filter delays the receive data by three System Clock cycles.
The FiltSatB signal is checked when the filtered RxD is sampled in the center of the bit
time. The presence of noise (
pled data is incorrect, just that the filter is not in its "saturated" state of all 1’s or all 0’s. If
FiltSatB = 1 when RxD is sampled during a receive character, the
tus[4:0]
work can be obtained.
Noise Filter Control (
counter digital filter. The available widths range from 4 bits to 11 bits.
The digital filter output features hysteresis
Provides an active low Saturated State output (
tion of the presence of noise.
and switches from 0 to 1 when the counter counts up from
A 2-bit counter is shown for convenience, the operation of wider counters is similar.
field is set. By observing this bit, an indication of the level of noise in the net-
Figure 17. Noise Filter System Block Diagram
NFEN, NFCTL
FiltSatB
RxD
TxD
NFCTL[2:0]
P R E L I M I N A R Y
FiltSatB = 1
Noise
Filter
) input selects the width of the up/down saturating
at center of bit time) does not mean the sam-
FiltSatB
GPIO
RxD
TxD
) which is used as an indica-
10b
NE
RxD
TxD
bit in the
to
Transceiver
11b.
LIN
PS024604-1005
00b
The noise
ModeSta-
01b
and
to