Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 195

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

PS024604-1005
1. The software initializes the
2. The software asserts the
3. The I
4. The software responds to the TDRE interrupt by writing the first slave address byte
5. The software asserts the
6. The I
7. The I
8. After one bit of the address is shifted out by the SDA signal, the transmit interrupt
9. The software responds by writing the second byte of address into the contents of the
10. The I
11. The I
12. The I
13. The I
14. The software responds by writing the data to be written out to the I
15. The I
SLAVE mode with 7- or 10-bit addressing (the I
slave address types). The
addressed as a slave (but not for the remote slave). The software asserts the IEN bit in
the I
rupts.
(
ister.
asserts.
I
out via the SDA signal.
high period of SCL. The I
If the slave does not acknowledge the first address byte, the I
NCKI bit in the I
State Register. The software responds to the Not Acknowledge interrupt by setting the
STOP
from the data register, sends a
NCKI
ister (2nd address byte).
first bit has been sent, the transmit interrupt asserts.
ter.
ensuing data bytes, if looping) via the SDA signal.
11110xx0
2
C Data Register.
2
2
2
2
2
2
2
2
2
C Control Register.
bit and clearing the
bits. The transaction is complete, and the following steps can be ignored.
C interrupt asserts because the I
C controller sends a
C controller loads the I
C controller shifts the remainder of the first byte of the address and the Write bit
C slave sends an Acknowledge by pulling the SDA signal Low during the next
C controller loads the I
C controller shifts the second address byte out via the SDA signal. After the
C controller shifts out the remainder of the second byte of the slave address (or
). The least-significant bit must be 0 for the write operation.
2
C Status Register, sets the
P R E L I M I N A R Y
TXI
START
MODE
TXI
2
START
C controller sets the ACK bit in the I
MODE
bit of the I
2
2
C Shift Register with the contents of the I
C Shift Register with the contents of the I
STOP
bit. The I
field selects the address width for this mode when
bit of the I
field in the I
condition to the I
condition on the bus, and clears the
2
C Data Register is empty.
2
2
C Control Register to enable transmit inter-
C controller flushes the second address byte
2
C Control Register.
ACKV
2
C Mode Register for MASTER/
2
C bus protocol allows the mixing of
bit, and clears the
2
C slave.
Product Specification
2
C controller sets the
2
C Status Register.
2
Master Transactions
C Control Regis-
ACK
2
2
bit in the I
STOP
C Data Reg-
C Data Reg-
and
2
C
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