Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 197

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

PS024604-1005
S
Slave Address
1st Byte
Figure 31. Data Transfer Format—Master Read Transaction with a 10-Bit Address
7. The I
8. The I
9. The I
10. The software responds by reading the I
11. The I
12. If there are more bytes to transfer, the I
13. A NAK interrupt (
14. The software responds by setting the STOP bit of the I
15. A
Master Read Transaction with a 10-Bit Address
Figure 31 illustrates the read transaction format for a 10-bit addressed slave.
The first seven bits transmitted in the first byte are
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
The data transfer procedure for a Read operation to a 10-bit addressed slave is as follows:
1. The software initializes the
2. The software writes
next high period of SCL.
If the slave does not acknowledge the address byte, the I
bit in the I
Register. The software responds to the Not Acknowledge interrupt by setting the
bit and clearing the
sends a
is complete, and the following steps can be ignored.
the final byte, the software must set the
final byte; otherwise, it sends an Acknowledge.
SLAVE mode with 7- or 10-bit addressing (the I
slave address types). The
addressed as a slave (but not for the remote slave). The software asserts the IEN bit in
the I
0 (write) to the I
W=0 A Slave Address
STOP
2
2
2
2
2
C Control Register.
C slave acknowledges the address by pulling the SDA signal Low during the
C controller shifts in the first byte of data from the I
C controller asserts the receive interrupt.
C controller sends a Not Acknowledge to the I
STOP
condition is sent to the I
2
C Status Register, sets the
condition on the bus, and clears the
2nd Byte
2
C Data Register.
NCKI
TXI
11110b
P R E L I M I N A R Y
bit. The I
bit in I2CISTAT) is generated by the I
MODE
A S Slave Address
MODE
, followed by the two most-significant address bits and a
field selects the address width for this mode when
2
C slave.
2
field in the I
C controller flushes the Transmit Data Register,
1st Byte
ACKV
2
2
C Data Register. If the next data byte is to be
NAK
C controller returns to Step 7.
bit, and clears the
bit of the I
2
11110XX
C Mode Register for MASTER/
2
STOP
C bus protocol allows the mixing of
R=1
2
C slave if the next byte is the
2
and
2
C Control Register.
C Control Register.
2
. The two
A
C controller sets the NCKI
2
C slave on the SDA signal.
NCKI
Product Specification
Data
ACK
2
C controller.
bits. The transaction
XX
bit in the I
Master Transactions
A
bits are the two
Data
2
C State
STOP
A P
175