Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 211

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

PS024604-1005
RESET
FIELD
ADDR
BITS
R/W
ACKV
R
7
0
Table 97. I
ACKV—ACK Valid
This bit is set if sending data (Master or Slave) and the
the byte just transmitted. This bit can be monitored if it is appropriate for software to ver-
ify the
register must not be written when
This bit clears when transmission of the next byte begins or the transaction is ended by a
STOP or RESTART condition.
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
This bit is set for an Acknowledge and cleared for a Not Acknowledge condition.
AS—Address State
This bit is active High while the address is being transferred on the I
DS—Data State
This bit is active high while the data is being transferred on the I
10B—This bit indicates whether a 10 or 7-bit address is being transmitted when operating
as a Master. After the
11110B
RSTR—RESTART
This bit is updated each time a STOP or RESTART interrupt occurs (
I2CISTAT register).
0 = Stop condition
1 = Restart condition
SCLOUT—Serial Clock Output
Current value of Serial Clock being output onto the bus. The actual values of the SCL and
SDA signals on the I2C bus can be observed via the GPIO Input register.
BUSY—I
0 = No activity on the I
1 = A transaction is underway on the I
ACK
, this bit is set. When set, it is reset once the address has been sent.
ACK
2
2
C Bus Busy
R
6
0
C State Register (I2CSTATE) - Description when DIAG = 0
value before writing the next byte to be sent. To operate in this mode, the data
START
AS
R
2
5
0
C Bus.
P R E L I M I N A R Y
bit is set, if the five most-significant bits of the address are
TDRE
DS
R
4
0
2
C bus.
F55H
asserts; instead, software waits for
10B
R
3
0
Z8FMC16100 Series Flash MCU
ACK
RSTR
R
2
0
bit in this register is valid for
Product Specification
2
C bus.
SCLOUT
2
SPRS
C bus.
R
X
1
I2C State Register
ACKV
bit set in
to assert.
BUSY
X
R
0
189