Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 194

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

172
Z8 Encore!
Product Specification
I2C Master/Slave Controller
S
Note:
Slave Address
Figure 29. Data Transfer Format—Master Write Transaction with a 10-Bit Address
1st Byte
®
Motor Control Flash MCUs
12. The I
13. The I
14. If more bytes remain to be sent, return to Step 9.
15. When there is no more data to be sent, the software responds by setting the
16. If no additional transaction is queued by the master, the software can clear the
17. The I
18. The I
If the slave terminates the transaction early by responding with a Not Acknowledge during
the transfer, the I
minate the transaction by setting either the
(end this transaction, start a new one). In this case, it is not necessary for software to set
the
transmitted. The I
acknowledge case.
Master Write Transaction with a 10-Bit Address
Figure 29 illustrates the data transfer format from a master to a 10-bit addressed slave.
The first seven bits transmitted in the first byte are
most significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
Read/Write control bit (which is cleared to 0). The transmit operation is performed in the
same manner as 7-bit addressing.
The procedure for a master transmit operation to a 10-bit addressed slave is as follows:
FLUSH
If the slave does not acknowledge the address byte, the I
bit in the I
Register. The software responds to the Not Acknowledge interrupt by setting the
bit and clearing the
sends a
is complete, and the following steps can be ignored.
I
transmit interrupt asserts.
the I
of the I
2
C Data Register.
2
2
2
2
2
C Control Register (or the
C controller loads the contents of the I
C controller shifts the data out via the SDA signal. After the first bit is sent, the
C controller completes transmission of the data on the SDA signal.
C controller sends a
bit of the I2CCTL Register to flush the data that was previously written but not
2
W=0
STOP
C Control Register.
2
C Status Register, sets the
2
condition on the bus, and clears the
2
C controller asserts the
C controller hardware automatically flushes transmit data in this not
A
TXI
Slave Address
P R E L I M I N A R Y
2nd Byte
bit. The I
STOP
START
condition to the I
2
C controller flushes the Transmit Data Register,
NCKI
ACKV
A
STOP
bit to initiate a new transaction).
interrupt and halts. The software must ter-
bit, and clears the
2
Data
bit (end transaction) or the
C Shift Register with the contents of the
11110XX
STOP
2
C bus.
A
and
2
. The two
C controller sets the NCKI
NCKI
Data
ACK
bits. The transaction
XX
bit in the I
bits are the two
A/A
PS024604-1005
START
STOP
2
C State
TXI
bit
STOP
F/S
bit of
bit