Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 200

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

178
Z8 Encore!
Product Specification
I2C Master/Slave Controller
®
Motor Control Flash MCUs
General Call and Start Byte Address Recognition.
address phase, and the controller is configured for MASTER/SLAVE or SLAVE in either
7- or 10-bit address modes, the hardware detects a match to the General Call Address or
the START byte and generates the slave address match interrupt. A General Call Address
is a 7-bit address of all 0’s with the R/W bit = 0. A START byte is a 7-bit address of all 0’s
with the R/W bit = 1. The
the I2CISTAT Register distinguishes a General Call Address from a START byte which is
cleared to 0 for a General Call Address). For a General Call Address, the I
automatically responds during the address acknowledge phase with the value in the
bit of the I2CCTL Register. If the software is set to process the data bytes associated with
the
ware to examine each received data byte before deciding to set or clear the
A START byte will not be acknowledged—a requirement of the I
Software Address Recognition.
must be set to 1 prior to the reception of the address byte(s). When
byte generates a receive interrupt (
examine each byte and determine whether to set or clear the
Low during the Acknowledge phase until the software responds by writing to the I2CCTL
Register. The value written to the
then releasing the SCL. The
phase, but the
Slave Transaction Diagrams
In the following transaction diagrams, the shaded regions indicate data transferred from
the master to the slave, and the unshaded regions indicate the data transferred from the
slave to the master. The transaction field labels are defined as follows:
Slave Receive Transaction with 7-Bit Address
The data transfer format for writing data from a master to a slave in 7-bit address mode is
shown in Figure 32. The procedure that follows describes the I
operating as a slave in 7-bit addressing mode and receiving data from the bus master.
S
W
A
A
P
GCA
Start
Write
Acknowledge
Not Acknowledge
Stop
bit, the
RD
IRM
bit is updated based on the first address byte.
bit can optionally be set following the
SAM
P R E L I M I N A R Y
SAM
and
and
NAK
RDRF
To disable hardware address recognition, the
GCA
GCA
bit is used by the controller to drive the I
bits are set in the I2CISTAT Register. The
= 1 in the I2CISTAT Register). The software must
bits are not set when
If
GCE
SAM
NAK
= 1 and
2
IRM
C Master/Slave Controller
interrupt to allow the soft-
bit. The slave holds SCL
2
C specification.
IRM
= 1 during the address
IRM
= 1, each received
= 0 during the
2
C controller
NAK
PS024604-1005
2
IRM
bit.
C bus,
RD
NAK
bit in
bit