Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 144

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

122
Z8 Encore!
Product Specification
LIN-UART
®
Motor Control Flash MCUs
LIN MASTER Mode Operation
LIN MASTER mode is selected by setting
=
LinState
The Break is the first part of the message frame transmitted by the master, consisting of at
least 13 bit periods of logical zero on the LIN bus. During initialization of the LIN master,
the duration (in bit times) of the Break is written to the
Control Register. The transmission of the Break is performed by setting the
Control 0 Register. The LIN-UART starts the Break once the
acter transmission currently underway has completed. The
ware once the break is completed.
The Synch character is transmitted by writing a
must = 1 before writing). The Synch character is not transmitted by the hardware until
after the Break is complete.
The Identifier character is transmitted by writing the appropriate value to the Transmit
Data Register (
If the master is sending the response portion of the message, these data and checksum
characters are written to the Transmit Data Register when the
mit data register is written after
one or two stop bits between each character as determined by the
register. Additional idle time occurs between characters if
character is written.
If the selected slave is sending the response portion of the frame to the master, each
receive byte will be signalled by the receive data interrupt (
Status0 register).
If the selected slave is sending the response to a different slave, the master can ignore the
response characters by deasserting the
slot has completed.
LIN Sleep Mode
While the LIN bus is in the sleep state, the CPU can be in either low power STOP mode, in
HALT mode, or in normal operational state. Any device on the LIN bus may issue a Wake-
up message if it requires the master to initiate a LIN message frame. Following the Wake-
up message, the master wakes up and initiates a new message. A Wake-up message is
accomplished by pulling the bus low for at least 250 µs but less than 5 ms. Transmitting a
00h
If the CPU is in STOP mode, the LIN-UART is not active and the Wake-up message must
be detected by a GPIO edge detect Stop-Mode Recovery. The duration of the Stop-Mode
Recovery sequence may preclude making an accurate measurement of the Wake-up mes-
sage duration.
11B.
character is one way to transmit the wake-up message.
If the LIN bus protocol indicates the bus is required go into the LIN sleep state, the
[1:0] bits must be set =
TDRE
must = 1 before writing).
P R E L I M I N A R Y
TDRE
00B
asserts, but before
REN
by software.
LMST
bit in the Control0 register until the frame time
55H
= 1,
to the Transmit Data Register (
LSLV
TxBreakLength
TXE
TXE
= 0,
SBRK
RDA
SBRK
TDRE
asserts, the hardware inserts
asserts before the next
ABEN
bit will be set in the
bit is deasserted by hard-
Stop
bit asserts. If the trans-
bit is set and any char-
= 0,
bit in the Control0
LinState
field of the LIN
SBRK
PS024604-1005
bit in the
TDRE
[1:0]