Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 146

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

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Z8 Encore!
Product Specification
LIN-UART
Note:
LIN-UART Interrupts
®
Motor Control Flash MCUs
If the Identifier character indicates that this slave device is not participating in the mes-
sage, software can set the
of the message. No further receive interrupts will occur until the next Break.
The LIN-UART features separate interrupts for the transmitter and receiver. In addition,
when the LIN-UART primary functionality is disabled, the Baud Rate Generator can also
function as a basic timer with interrupt capability.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(
mission. The TDRE interrupt occurs when the transmitter is initially enabled and after the
Transmit shift register has shifted the first bit of a character out. At this point, the Transmit
Data Register may be written with the next character to send. This provides 7 bit periods
of latency to load the Transmit Data Register before the Transmit shift register completes
shifting the current character. Writing to the LIN-UART Transmit Data Register clears the
TDRE
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
•
In MULTIPROCESSOR mode (
the multiprocessor configuration and the most recent address byte
•
•
•
•
LIN-UART Overrun Errors
When an overrun error condition occurs the LIN-UART prevents overwriting of the valid
data currently in the Receive Data Register. The Break Detect and Overrun status bits are
not displayed until after the valid data has been read.
TDRE
A data byte has been received and is available in the LIN-UART Receive Data Regis-
ter. This interrupt can be disabled independent of the other receiver interrupt sources
via the
data interrupt occurs once the receive character has been placed in the Receive Data
Register. Software must respond to this received data available condition before the
next character is completely received to avoid an overrun error.
A break is received
A receive data overrun or LIN slave autobaud overrun error is detected.
A data framing error is detected
A parity error is detected (physical layer error in LIN mode)
bit to 0.
) is set to 1. This indicates that the transmitter is ready to accept new data for trans-
RDAIRQ
bit (this feature is useful in devices which support DMA). The received
LinState[1:0]
P R E L I M I N A R Y
MPEN
= 1), the receive data interrupts are dependent on
=
01b
(Wait for Break State) to ignore the rest
PS024604-1005