Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 207

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

PS024604-1005
RESET
FIELD
ADDR
BITS
R/W
TDRE
R
7
1
Table 93. I
TDRE—Transmit Data Register Empty
When the I
When set, this bit causes the I
Controller is shifting in data during the reception of a byte or when shifting an address and
the RD bit is set. This bit clears by writing to the I2CDATA register.
RDRF—Receive Data Register Full
This bit is set = 1 when the I
byte of data. When asserted, this bit causes the I
This bit clears by reading the I2CDATA register.
SAM—Slave Address Match
This bit is set = 1 if the I
which matches the unique Slave address or General Call Address (if enabled by the
bit in the I
achieved on both address bytes. When this bit is set, the
This bit clears by reading the I2CISTAT register.
GCA—General Call Address
This bit is set in Slave mode when the General Call Address or START byte is recognized
(in either 7 or 10 bit Slave mode). The
enable recognition of the General Call Address and START byte. This bit clears when
= 0 and is updated following the first address byte of each Slave mode transaction. A Gen-
eral Call Address is distinguished from a START byte by the value of the RD bit (RD = 0
for General Call Address, 1 for START byte).
RD—Read
This bit indicates the direction of transfer of the data. It is set when the Master is reading
data from the Slave. This bit matches the least-significant bit of the address byte after the
START condition occurs (for both Master and Slave modes). This bit clears when IEN = 0
and is updated following the first address byte of each transaction.
ARBLST—Arbitration Lost
This bit is set when the I
(outputs a 1 on SDA and receives a 0 on SDA). The ARBLST bit clears when the
I2CISTAT register is read.
RDRF
2
2
2
R
6
0
C Mode register). In 10-bit addressing mode, this bit is not set until a match is
C Interrupt Status Register (I2CISTAT)
C Controller is enabled, this bit is 1 when the I
SAM
R
5
0
2
2
C Controller is enabled in Slave mode and an address is received
C Controller is enabled in Master mode and loses arbitration
P R E L I M I N A R Y
2
C Controller is enabled and the I
2
C Controller to generate an interrupt, except when the I
GCA
R
4
0
GCE
F51H
bit in the I
RD
R
3
0
2
C Controller to generate an interrupt.
Z8FMC16100 Series Flash MCU
2
C Mode register must be set to
ARBLST
RD
2
R
2
0
C Data register is empty.
and
2
C Controller has received a
GCA
I2C Interrupt Status Register
Product Specification
bits are also valid.
SPRS
R
1
0
NCKI
R
0
0
GCE
IEN
2
C
185