Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 192

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

170
Z8 Encore!
Product Specification
I2C Master/Slave Controller
®
Motor Control Flash MCUs
Master Arbitration
If a master loses arbitration during the address byte, it releases the SDA line, switches to
SLAVE mode and monitors the address to determine if it is selected as a slave. If a master
loses arbitration during the transmission of a data byte, it releases the SDA line and waits
for the next
The master detects a loss of arbitration when a 1 is transmitted but a 0 is received from the
bus in the same bit-time. This loss occurs if more than one master is simultaneously
accessing the bus. Loss of arbitration can occur during the address phase (two or more
masters accessing different slaves) or during the data phase, when the masters are attempt-
ing to write different data to the same slave.
When a master loses arbitration, the software is informed by means of the Arbitration Lost
interrupt. The software can repeat the same transaction at a later time.
A special case can occur when a slave transaction starts just before the software attempts
to start a new master transaction by setting the
enters its slave states before the
arbitrate. If a slave address match occurs and the I
START
mize the chance of this instance occurring by checking the
Register before initiating a master transaction. If a slave address match does not occur, the
Arbitration Lost interrupt will not occur, and the
controller will initiate the master transaction after the I
Master Address-Only Transactions
It is sometimes preferable to perform an address-only transaction to determine if a particu-
lar slave device is able to respond. This transaction can be performed by monitoring the
ACKV
Register and the
I2CSTATE Register determines if the slave is able to communicate. The
set in the I2CCTL Register to terminate the transaction without transferring data. For a 10-
bit slave address, if the first address byte is acknowledged, the second address byte should
also be sent to determine if the preferred slave is responding.
Another approach is to set both the
After both bits have cleared (7-bit address has been sent and transaction is complete), the
ACK
STOP
being sent).
Master Transaction Diagrams
In the following transaction diagrams, the shaded regions indicate the data that is trans-
ferred from the master to the slave, and the unshaded regions indicate the data that is trans-
ferred from the slave to the master. The transaction field labels are defined as follows:
bit can be read to determine if the slave has acknowledged. For a 10-bit slave, set the
bit in the I2CSTATE Register after the address has been written to the I2CDATA
bit after the second TDRE interrupt (which indicates that the second address byte is
bit is cleared and an Arbitration Lost interrupt is asserted. The software can mini-
STOP
START
or
START
bit has been set. After the
P R E L I M I N A R Y
condition.
START
STOP
bit is set, and as a result, the I
and
START
START
START
2
C controller receives/transmits data, the
ACKV
bits (for sending a 7-bit address).
bit. In this case, the state machine
2
C bus is no longer busy.
bit will not be cleared. The I
bit is set, the
BUSY
bit in the I2CSTATE
2
C controller will not
ACK
STOP
bit in the
PS024604-1005
bit must be
2
C