Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 199

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

PS024604-1005
Slave Transactions
17. The I
18. The I
19. The I
20. The I
21. The I
22. The software responds by reading the I
23. The I
24. If there are more bytes to transfer, the I
25. The I
26. The software responds by setting the
27. A
The following sections describe Read and Write transactions to the I
ured for 7- and 10-bit slave modes.
Slave Address Recognition
The following slave address recognition options are supported.
Slave 7-Bit Address Recognition Mode.
controller is configured for MASTER/SLAVE or SLAVE 7-bit address mode, the hard-
ware detects a match to the 7-bit slave address defined in the I2CSLVAD Register and
generates the slave address match interrupt (
The I
in the
Slave 10-Bit Address Recognition Mode.
controller is configured for MASTER/SLAVE or SLAVE 10-bit address mode, the hard-
ware detects a match to the 10-bit slave address defined in the I2CMODE and I2CSLVAD
registers and generates the slave address match interrupt (the
Register). The I
the value in the
ister (the third address transfer).
slave read address and a 1 (Read).
High period of SCL.
the final byte, the software must set the
on the value of the
ter).
2
NAK
C controller automatically responds during the Acknowledge phase with the value
STOP
2
2
2
2
2
2
2
C controller loads the I
C controller sends
C slave sends an Acknowledge by pulling the SDA signal Low during the next
C controller shifts in a byte of data from the slave.
C controller asserts the Receive interrupt.
C controller sends an Acknowledge or Not Acknowledge to the I
C controller generates a NAK interrupt (the
bit of the I2CCTL Register.
condition is sent to the I
2
NAK
C controller automatically responds during the Acknowledge phase with
bit of the I2CCTL Register.
NAK
P R E L I M I N A R Y
bit.
11110b
2
C Shift Register with the contents of the I
2
, followed by the two most-significant bits of the
C slave.
STOP
If
2
2
C Data Register. If the next data byte is to be
NAK
C controller returns to Step 18.
If
the SAM
IRM
IRM
bit of the I
bit of the I
= 0 during the address phase and the
= 0 during the address phase and the
bit = 1 in the I2CISTAT Register).
NCKI
2
C Control Register.
2
C Control Register.
bit in the I2CISTAT Regis-
SAM
Product Specification
bit = 1 in the I2CISTAT
2
C controller config-
Slave Transactions
2
C slave, based
2
C Data Reg-
177