AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 83

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

9.5.2.1
9.5.3
9.5.4
32099A–AVR32–06/09
Lock Mechanism
Normal Operation
Protecting SAU configuration registers
In order to prevent the SAU configuration registers to be changed by malicious or runaway
code, they should be protected by the MPU as soon as they have been configured. Maximum
security is provided in the system if program memory does not contain any code to unprotect
the configuration registers in the MPU. This guarantees that runaway code can not acciden-
tally unprotect and thereafter change the SAU configuration registers.
The SAU can be configured to use two different access mechanisms: Open and Locked. In
Open Mode, SAU channels can be accessed freely after they have been configured and
enabled. In order to prevent accidental accesses to remapped addresses, it is possible to con-
figure the SAU in Locked Mode. Writing a one to the Open Mode bit in the CONFIG register
(CONFIG.OPEN) will enable Open Mode. Writing a zero to CONFIG.OPEN will enable Locked
Mode.
When using Locked Mode, the lock mechanism must be configured by writing a user defined
key value to the Unlock Key (UKEY) field in the Configuration Register (CONFIG). The num-
ber of CLK_SAU_HSB cycles the channel remains unlocked must be written to the Unlock
Number of Clock Cycles (UCYC) field in CONFIG.
Access control to the SAU channels is enabled by means of the Unlock Register (UR), which
resides in the same address space as the SAU channels. Before a channel can be accessed,
the unlock key value must be written to UR.KEY, and the channel number to UR.CHANNEL.
Access to the channel is then permitted for the next CONFIG.UCYC clock cycles, or until a
successful access to the unlocked channel has been made.
Only one channel can be unlocked at a time. If any other channel is unlocked at the time of
writing UR, this channel will be automatically locked before the channel addressed by the UR
write is unlocked.
An attempted access to a locked channel will be aborted, and the Channel Access Unsuc-
cessful bit (SR.CAU) will be set.
Any pending errors bits in SR must be cleared before it is possible to access UR. The follow-
ing SR bits are defined as error bits: EXP, CAU, URREAD, URKEY, URES, MBERROR,
RTRADR. If any of these bits are set while writing to UR, the write is aborted and the Unlock
Register Error Status (URES) bit in SR is set.
The following sequence must be used in order to access a SAU channel in normal operation
(CR.SEN=0):
1. If not in Open Mode, write the unlock key to UR.KEY and the channel number to
2. Perform the read or write operation to the SAU channel. If not in Open Mode, this
3. To confirm that the access was successful, wait for the IDLE transfer status bit
UR.CHANNEL.
must be done within CONFIG.UCYC clock cycles of unlocking the channel. The SAU
will use its HSB master interface to remap the access to the target address pointed to
by the corresponding RTR.
(SR.IDLE) to indicate the operation is completed. Then check SR for possible error
conditions. The SAU can be configured to generate interrupt requests or a Bus Error
Exception if the access failed.
AT32UC3L
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