AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 254

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

15.5.2.3
15.5.3
15.5.3.1
32099A–AVR32–06/09
Interrupts
Calendar operation
Periodic interrupt
When the CAL bit in the Control Register is one, the counter operates in calendar mode. Before
this mode is enabled, the prescaler should be set up to give a pulse every second. The date and
time can then be read from or written to the Calendar Value (CALV) register.
Time is reported as seconds, minutes, and hours according to the 24-hour clock format. Date is
the numeral date of month (starting on 1). Month is the numeral month of the year (1 = January,
2 = February, etc.). Year is a 6-bit field counting the offset from a software-defined leap year
(e.g. 2000). The date is automatically compensated for leap years, assuming every year divisible
by 4 is a leap year.
All peripheral events and interrupts work the same way in calendar mode as in counter mode.
However, the Alarm Register (ARn) must be written in time/date format for the alarm to trigger
correctly.
The AST can generate five separate interrupt requests:
This allows the user to allocate separate handlers and priorities to the different interrupt types.
The generation of the PER interrupt is described in
ALARM interrupt is described in
counter overflows, or when the alarm value is reached, if the Clear on Alarm bit in the Control
Register is one. The CLKREADY interrupt is generated when SR.CLKBUSY has a 1-to-0 transi-
tion, and indicates that the clock synchronization is completed. The READY interrupt is
generated when SR.BUSY has a 1-to-0 transition, and indicates that the synchronization
described in
An interrupt request will be generated if the corresponding bit in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared
by writing a one to the corresponding bit in the Status Clear Register (SCR).
The AST interrupts can wake the CPU from any sleep mode where the source clock and the
interrupt controller is active.
The AST can generate periodic interrupts. If the PERn bit in the Interrupt Mask Register (IMR) is
one, the AST will generate an interrupt request on the 0-to-1 transition of the selected bit in the
prescaler when the AST is enabled. The bit is selected by the Interval Select field in the corre-
sponding Periodic Interval Register (PIRn.INSEL), resulting in a periodic interrupt frequency of
where f
The corresponding PERn bit in the Status Register (SR) will be set when the selected bit in the
the prescaler has a 0-to-1 transition.
• OVF: OVF
• PER: PER0, PER1
• ALARM: ALARM0, ALARM1
• CLKREADY
• READY
CS
is the frequency of the selected clock source.
Section 15.5.8
is completed.
Section
15.5.3.2. The OVF interrupt is generated when the
Section
15.5.3.1., and the generation of the
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