AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 339

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

19.6.2.10
19.6.2.11
32099A–AVR32–06/09
Peripheral Events
CPU Local Bus
The CPU Local Bus can be used for application where low latency read and write access to the
Output Value Register (OVR) and Output Drive Enable Register (ODER) is required. The CPU
Local Bus allows the CPU to configure the mentioned GPIO registers directly, bypassing the
shared Peripheral Bus (PB).
To avoid data loss when using the CPU Local Bus, the CLK_GPIO must run at the same fre-
quency as the CLK_CPU. See
The CPU Local Bus is mapped to a different base address than the GPIO but the OVER and
ODER offsets are the same. See the CPU Local Bus Mapping section in the Memories chapter
for details.
Peripheral events allow direct peripheral to peripheral communication of specified events. See
the Peripheral Event System chapter for more information.
The GPIO can be programmed to output peripheral events whenever an interrupt condition is
detected, such as pin value change, or only when a rising or falling edge is detected. Peripheral
event on a pin is enabled by writing a one to the corresponding bit in the Event Enable Register
(EVER). The Peripheral Event trigger mode is shared with the interrupt trigger and is configured
by writing to the IMR0 and IMR1 registers. Interrupt does not need to be enabled on a pin when
peripheral events are enabled. Peripheral Events are also affected by the Input Glitch Filter set-
tings. See
A peripheral event can be generated on each GPIO pin. Each port can then have up to 32
peripheral event generators. Groups of eight peripheral event generators in each port are ORed
together to form a peripheral event line, so that each port has four peripheral event lines con-
nected to the Peripheral Event System.
Section 19.6.2.8
for more information.
Section 19.5.2
for details.
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