AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 608

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

26.4
Table 26-1.
26.5
26.5.1
26.5.2
26.5.3
32099A–AVR32–06/09
Pin Name
VDDANA
ADVREF
ADTRG
RND
DP0
DP1
AD0-ADn
I/O Lines Description
Product Dependencies
I/O Lines
Power Management
Clocks
I/O Lines Description
In order to use this module, other parts of the system must be configured correctly, as described
below.
The analog input pins can be multiplexed with I/O Controller lines. The user must make sure the
I/O Controller is configured correctly to allow the ADCIFB access to the AD pins before the
ADCIFB is instructed to start converting data. If the user fails to do this the converted data may
be wrong.
The number of analog inputs is device dependent, please refer to the ADCIFB Module Configu-
ration chapter for the number of available AD inputs on the current device.
The VDDANA and ADVREF pins must be connected correctly prior to using the ADCIFB. Failing
to do so will result in invalid ADC operation. See the Electrical Characteristics chapter for details.
If the ADTRG, RND, DP0, and DP1 pins are to be used in the application, the user must config-
ure the I/O Controller to assign the needed pins to the ADCIFB function.
If the CPU enters a sleep mode that disables clocks used by the ADCIFB, the ADCIFB will stop
functioning and resume operation after the system wakes up from sleep mode.
If the Periperhal Event System is configured to send asynchronous peripheral events to the
ADCIFB and the clock used by the ADCIFB is stopped, a local and temporary clock will automat-
ically be requested so the event can be processed. Refer to
and the Peripheral Event System chapter for details.
Before entering a sleep mode where the clock to the ADCIFB is stopped, make sure the Analog-
to-Digital Converter cell is put in an inactive state. Refer to
The clock for the ADCIFB bus interface (CLK_ADCIFB) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the ADCIFB before disabling the clock, to avoid freezing the ADCIFB in an undefined
state.
Description
Analog power supply
Reference voltage
External trigger
A pseudorandom output
Drive Pin 0 for Touch Screen top channel (Xp)
Drive Pin 1 for Touch Screen right channel (Yp)
Analog input channels 0 to n
Section 26.6.14
Section
26.6.14,
Digital
Type
Power
Analog
Digital
Digital
Digital
Analog
for more information.
AT32UC3L
Section
26.6.13,
608