AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 153

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

13. Power Manager (PM)
13.1
13.2
32099A–AVR32–06/09
Features
Overview
Rev: 4.1.1.0
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The Power Manager (PM) provides synchronous clocks used to clock the main digital logic in the
device, namely the CPU, and the modules and peripherals connected to the High Speed Bus
(HSB) and the Periperal Buses (PBx).
The PM also contains advanced power-saving features, allowing the user to optimize the power
consumption for an application. The synchronous clocks are divided into a number of clock
domains, one for the CPU and HSB and one for each PBx. The clocks can run at different
speeds, so the user can save power by running peripherals at a relatively low clock, while main-
taining a high CPU performance. Additionally, the clocks can be independently changed on-the-
fly, without halting any peripherals. This enables the user to adjust the speed of the CPU and
memories to the dynamic load of the application, without disturbing or re-configuring active
peripherals.
Each module also has a separate clock, enabling the user to switch off the clock for inactive
modules, to save further power. Additionally, clocks and oscillators can be automatically
switched off during idle periods by using the sleep instruction on the CPU. The system will return
to normal operation on occurrence of interrupts.
To get maximum power savings, a special sleep mode, called Shutdown is available, where
power on all internal logic (CPU, peripherals) and most of the I/O lines is removed, reducing
leakage. Only a small amount of logic, including 32KHz crystal oscillator and AST is left
powered.
The Power Manager also contains a Reset Controller, which collects all possible reset sources,
generates hard and soft resets, and allows the reset source to be identified by software.
Generates clocks and resets for digital logic
On-the-fly frequency change of CPU, HSB and PBx clocks
Sleep modes allow simple disabling of logic clocks and clock sources
Module-level clock gating through maskable peripheral clocks
Wake-up from internal or external interrupts
Automatic identification of reset sources
Support advanced Shutdown sleep mode
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