AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 144

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

12.4
12.4.1
12.4.2
12.4.3
12.5
32099A–AVR32–06/09
Product Dependencies
Functional Description
Power Management
Clocks
Debug Operation
Figure 12-1. INTC Block Diagram
In order to use this module, other parts of the system must be configured correctly, as described
below.
If the CPU enters a sleep mode that disables clocks used by the INTC, the INTC will stop func-
tioning and resume operation after the system wakes up from sleep mode.
The clock for the INTC bus interface (CLK_INTC) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager.
When an external debugger forces the CPU into debug mode, the INTC continues normal
operation.
All of the incoming interrupt requests (IREQs) are sampled into the corresponding Interrupt
Request Register (IRR). The IRRs must be accessed to identify which IREQ within a group that
is active. If several IREQs within the same group are active, the interrupt service routine must
prioritize between them. All of the input lines in each group are logically ORed together to form
the GrpReqN lines, indicating if there is a pending interrupt in the corresponding group.
The Request Masking hardware maps each of the GrpReq lines to a priority level from INT0 to
INT3 by associating each group with the Interrupt Level (INTLEVEL) field in the corresponding
Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the
CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not
masked by the CPU status register, gets its corresponding ValReq line asserted.
NMIREQ
IREQ63
IREQ34
IREQ33
IREQ32
IREQ31
IREQ2
IREQ1
IREQ0
IRR Registers
Interrupt Controller
OR
OR
OR
IRRn
IRR1
IRR0
GrpReq1
GrpReq0
GrpReqN
.
.
.
Request
Masking
ValReqN
ValReq1
ValReq0
IPRn
IPR1
IPR0
.
.
.
IPR Registers
INT_level,
INT_level,
INT_level,
offset
offset
offset
.
.
.
ICR Registers
AUTOVECTOR
AT32UC3L
INTLEVEL
Masks
CPU
I[3-0]M
SREG
Masks
GM
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