AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 807

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

35.2.7
32099A–AVR32–06/09
SCIF
6. Clock failure detector does not work
1. A reset from Supply Monitor 33 will be registered as POR
2. The DFLL should be slowed down before disabled
3. Writing to SCIF ICR masks new interrupts received in the same clock cycle
4. FINE value for DFLL is not correct when dithering is disabled
5. BODVERSION register reads 0x100
7. BRIFA is non-functional
8. VREGCR DEEPMODEDISABLE bit is not readable
9. DFLL step size should be 7 or lower below 30 MHz
In some cases the clock failure detector will not detect if the CPU clock stops. In this case
the CPU will halt operation.
Fix/Workaround
None.
A Supply Monitor 33 reset will not be detected in the Reset Cause register (RCAUSE) as
BOD33, it will be detected as a Power-on Reset (POR).
Fix/Workaround
None.
The frequency of the DFLL should be set to minimum before disabled.
Fix/Workaround
Before disabling the DFLL the value of the COARSE register should be set to
zero.
Writing to SCIF ICR masks any new SCIF interrupt received in the same clock
cycle, regardless of write value.
Fix/Workaround:
For every interrupt except BODDET, SM33DET, and VREGOK the CLKSR register can be
read to detect new interrupts. BODDET, SM33DET and VREGOK interrupts will not be gen-
erated if they occur when writing SCIF ICR.
In open loop mode, the FINE value used by the DFLL DAC is offseted by two compared to
the value written to the DFLL0CONF.FINE field. I. e. the value to the DFLL DAC is
DFLL0CONF.FINE-0x002. If DFLL0CONF.FINE is written to 0x000, 0x001 or 0x002 the
value to the DFLL DAC will be 0x1FE, 0x1FF or 0x000 respectively.
Fix/workaround
Write the desired value added by two to the DFLL0CONF.FINE field.
The BODVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
BRIFA is non-functional.
Fix/Workaround
None.
VREGCR DEEPMODEDISABLE bit is not readable.
Fix/workaround
None.
If max step size is above 7, the DFLL might not lock at the correct frequency if the target fre-
quency is below 30 MHz.
AT32UC3L
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