AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 548

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

24.5.1
24.5.2
24.5.3
24.5.4
24.5.5
24.5.6
24.6
24.6.1
24.6.2
32099A–AVR32–06/09
Functional Description
I/O Lines
Power Management
Clocks
Interrupts
Peripheral Events
Debug Operation
Enabling the PWMA
Timebase Counter
The pins used for interfacing the PWMA may be multiplexed with I/O Controller lines. The pro-
grammer must first program the I/O Controller to assign the desired PWMA pins to their
peripheral function.
It is only required to enable the PWMA outputs actually in use.
If the CPU enters a sleep mode that disables clocks used by the PWMA, the PWMA will stop
functioning and resume operation after the system wakes up from sleep mode.
The clock for the PWMA bus interface (CLK_PWMA) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the PWMA before disabling the clock, to avoid freezing the PWMA in an undefined state.
Additionally, the PWMA depends on a dedicated Generic Clock (GCLK). The GCLK can be set
to a wide range of frequencies and clock sources and must be enabled in the System Control
Interface (SCIF) before the PWMA can be used.
The PWMA interrupt request lines are connected to the interrupt controller. Using the PWMA
interrupts requires the interrupt controller to be programmed first.
The PWMA peripheral events are connected via the Peripheral Event System. Refer to the
Peripheral Event System chapter for details.
When an external debugger forces the CPU into debug mode, the PWMA continues normal
operation. If the PWMA is configured in a way that requires it to be periodically serviced by the
CPU through interrupts, improper operation or data loss may result during debugging.
The PWMA embeds a number of PWM channel submodules, each providing an output PWM
waveform. Each PWM channel contains a duty cycle register and a comparator. A common
timebase counter for all channels determines the frequency and the period for all the PWM
waveforms.
Once the GCLK has been enabled, the PWMA is enabled by writing a one to the EN bit in the
Control Register (CR).
The top value of the timebase counter defines the period of the PWMA output waveform. The
timebase counter starts at zero when the PWMA is enabled and counts upwards until it reaches
its effective top value (ETV). The effective top value is defined by specifying the desired number
of GCLK clock cycles in the TOP field of CR (CR.TOP) in normal operation (CR.SPREAD is
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