AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 194

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

14.5.3.3
32099A–AVR32–06/09
Enabling the DFLL
The ratio between the reference clock and the VCO clock is measured automatically by the DFL-
LIF. The difference between this ratio and DFLL0MUL is stored in the Multiplication Ratio
Difference field (RATIODIFF) in the DFLL0RATIO register. To get the result on the same form as
DFLL0MUL, the error must be calculated as follows:
where
ratio. The DFLL0RATIO register is only updated every time the Synchronization (SYNC) bit in
DFLL0SYNC is written to one; refer to DFLL0SYNC register description for details.
Figure 14-3. DFLL Closed Loop State Diagram
Figure 14-4. DFLL Locking in Closed Loop
Before configuring the DFLL, only the EN bit in the DFLL0CONF register should be written to
one. Writes to other bits in DFLL0CONF will be ignored. The DFLL is now ready for
configuration.
2
NUMREF
DFLLLOCKC
frequency
COARSE
Calculate
Measure
is the number of reference clock cycles the DFLLIF is using for calculating the
value
VCO
new
0
f
f
t
o
1
f
overflow
t
coarse
DFLLLOCKF
new FINE
Calculate
value
0
LOCKC
f
coarse
error
1
t
fine
=
LOCKF
RATIODIFF
-------------------------------- -
Compen-
DITHER
sate for
2
drift
0
NUMREF
f
fine
t
accurate
1
LOCKA
DFLLLOCKA
Calculate
dutycycle
dithering
new
0
AT32UC3L
1
Compen-
sate for
drift
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