AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 155
AT32UC3L064_1
Manufacturer Part Number
AT32UC3L064_1
Description
AVR32 32-bit Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT32UC3L064_1.pdf
(825 pages)
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13.6
13.6.1
Figure 13-2. Synchronous Clock Generation
13.6.1.1
13.6.1.2
32099A–AVR32–06/09
Main Clock
Sources
Functional Description
Synchronous Clocks
Selecting the main clock source
Selecting synchronous clock division ratio
MCSEL
The System RC Oscillatro (RCSYS) or a set of other clock sources provide the source for the
main clock, which is the common root for the synchronous clocks for the CPU/HSB and PBx
modules. For details about the other main clock sources, please refer to the register description
of the Main Clock Control Register (MCCTRL). The main clock is divided by an 8-bit prescaler,
and each of these four synchronous clocks can run from any tapping of this prescaler, or the
undivided main clock, as long as f
the fly, responding to varying load in the application. The clock domains can be shut down in
sleep mode, as described in
domains can be individually masked, to avoid power consumption in inactive modules.
The common main clock can be connected to RCSYS or a set of other clock sources. For details
about the other main clock sources, please refer to the register description of the Main Clock
Control Register (MCCTRL). By default, the main clock will be connected to RCSYS. The user
can connect the main clock to an other source by writing the MCSEL field in the MCCTRL regis-
ter. This must only be done after that unit has been enabled, otherwise a deadlock will occur.
Care should also be taken that the new frequency of the synchronous clocks does not exceed
the maximum frequency for each clock domain.
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks.
By default, the synchronous clocks run on the undivided main clock. The user can select a pres-
caler division for the CPU clock by writing CPUDIV in CPUSEL register to 1 and CPUSEL in
CPUSEL register to the value, resulting in a CPU clock frequency:
Prescaler
f
CPU
= f
Instruction
main
Sleep
/ 2
(CPUSEL+1)
CPUSEL
CPUDIV
Section
0
1
CPU
Controller
Main Clock
13.6.3. Additionally, the clocks for each module in the four
Sleep
≥ f
PBx,
. The synchronous clock source can be changed on-
CPUMASK
Mask
AT32UC3L
CPU Clocks
HSB Clocks
PBx Clocks
155
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