AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 45

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

32099A–AVR32–06/09
Figure 7-3.
Internally, the flash memory stores data in 64-bit doublewords. Therefore, the native data size
of the Page Buffer is also a 64-bit doubleword. All locations shown in
doubleword locations. Since the HSB bus only has a 32-bit data width, two 32-bit HSB trans-
fers must be performed to write a 64-bit doubleword into the Page Buffer. The FLASHCDW
has logic to combine two 32-bit HSB transfers into a 64-bit data before writing this 64-bit data
into the Page Buffer. This logic requires the word with the low address to be written to the HSB
bus before the word with the high address. To exemplify, to write a 64-bit value to doubleword
X0 residing in page X, first write a 32-bit word to the byte address pointing to address X0,
thereafter write a word to the byte address pointing to address (X0+4).
The page buffer is word-addressable and should only be written with aligned word transfers,
never with byte or halfword transfers. The page buffer can not be read.
The page buffer is also used for writes to the User page.
Page buffer write operations are performed with 4 wait states. Any accesses attempted to the
FLASHCDW on the HSB bus during these cycles will be automatically stalled.
Writing to the page buffer can only change page buffer bits from one to zero, i.e. writing
0xAAAAAAAA to a page buffer location that has the value 0x00000000 will not change the
page buffer value. The only way to change a bit from zero to one is to erase the entire page
buffer with the Clear Page Buffer command.
All locations are doubleword locations
31
27
23
19
15
11
7
3
Page Buffer
30
26
22
18
14
10
64-bit data
6
2
Mapping from Page Buffer to Flash
29
25
21
17
13
9
5
1
28
24
20
16
12
8
4
0
Z31
Z27
Z23
Z19
Z15
Z11
Y31
Y27
Y23
Y19
Y15
Y11
X31
X27
X23
X19
X15
X11
Z7
Z3
Y7
Y3
X7
X3
Z30
Z26
Z22
Z18
Z14
Z10
Y30
Y26
Y22
Y18
Y14
Y10
X30
X26
X22
X18
X14
X10
Z6
Z2
Y6
Y2
X6
X2
Page Z
Page Y
Page X
Flash
Y29
Y25
Y21
Y17
Y13
X29
X25
X21
X17
X13
Z29
Z25
Z21
Z17
Z13
Z9
Z5
Z1
Y9
Y5
Y1
X9
X5
X1
Figure 7-3
AT32UC3L
Y28
Y24
Y20
Y16
Y12
X28
X24
X20
X16
X12
Z28
Z24
Z20
Z16
Z12
Y8
Y4
Y0
X8
X4
X0
Z8
Z4
Z0
are therefore
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