AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 193

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

14.5.3.2
32099A–AVR32–06/09
Closed Loop Operation
In closed loop mode the accuracy of the output frequency is limited by the accuracy of the refer-
ence clock. Set MODE and EN to one in DFLL0CONF register to enable the DFLL in closed loop
mode. The output frequency of the DFLL will be given by:
The COARSE and FINE fields in DFLL0CONF register are Read-only in closed loop mode, and
are controlled by the DFLL to meet user specified frequency. The values in the COARSE regis-
ter when the closed loop mode is enabled is used by the frequency tuner as a starting point for
the COARSE value. Setting the COARSE to a value believed to be the correct will reduce the
time needed to get a lock on the coarse value. To set up the DFLLIF first enable the DFLL by
writing one to EN bit in DFLL0CONF register. Then enable and select a reference clock
(CLK_DFLLIF_REF). CLK_DFLLIF_REF is a generic clock, please refer to Generic Clocks
chapter for details. Then set the maximum step size allowed in finding the COARSE and FINE
values by setting the CSTEP and FSTEP bits in DFLL0STEP register. A small step size will
ensure low overshoot on the output frequency, but will typically be slower. A high value might
give a big overshoot, but will typically give faster locking. DFLL0STEP.CSTEP and
DFLL0STEP.FSTEP should not be set higher than 50% of the maximum value of
DFLL0CONF.COARSE and DFLL0CONF.FINE respectively. Setting the max step size to 50%
of the max value will give a binary search. Then set the value of FMUL in DFLL0MUL register,
care must be taken when choosing FMUL so the output frequency does not exceed the maxi-
mum frequency of the device.
The locking of the frequency in closed loop mode is divided into three stages. In the COARSE
stage the control logic quickly finds the correct value for the COARSE field in DFLL0CONF reg-
ister and thereby setting the output frequency to a value close to the correct frequency. The
DFLL0LOCKC interrupt is issued when this is done. In the FINE stage the control logic tunes the
value in the FINE field in the DFLL0CONF register so the output frequency very close to the
desired frequency. The DFLL0LOCKF interrupt is issued when this is done. In the ACCURATE
stage the DFLL frequency tuning mechanism uses dithering on the FINE bits to obtain an accu-
rate output frequency. When the accurate frequency is obtained the DFLL0LOCKA interrupt is
issued. The ACCURATE stage will only be executed if DITHER bit in DFLL0CONF register is set
to one. If DITHER is set to zero DFLL0LOCKA will never occur. If dithering is enabled, the fre-
quency of the dithering is decided by a generic clock (CLK_DFLLIF_DITHER). This clock has to
be set up correctly before enabling dithering. Please refer to the Generic Clocks chapter for
details. The flow for finding the correct settings is shown in
When dithering is enable the accuracy of the average output frequency of the DFLL will be
higher. However, the frequency will be alternating between two frequencies. If a fixed frequency
is required, the dithering should not be enabled.
The frequency tuner will automatically compensate for drift in the output frequency of the VCO
without losing either of the locks. If the FINE register overflows or underflows, which should nor-
mally not happen, but could occur due to large drift in temperature and voltage, all locks will be
lost, and the COARSE and FINE values will be recalibrated as described earlier. When spread
spectrum is enabled and the AMPLITUDE is high, an overflow/underflow is more likely to occur.
If the reference clock stops, the DFLL0RCS interrupt will be asserted. Note that the detection of
the clock stop will take long time. The DFLL will enter open loop mode if it detects that the refer-
ence clock has stopped.
f
VCO
=
FMUL
---------------- - f
2
16
ref
Figure 14-3 on page
AT32UC3L
194.
193