AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 526

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

23.8.6.2
23.8.6.3
23.8.7
23.8.8
32099A–AVR32–06/09
Wakeup from Sleep Modes by TWI Address Match
Identifying Bus Events
Timeouts
SMBALERT
pare it to the PEC value it has computed itself. If the values match, the data was received
correctly. If the PEC values differ, data was corrupted, and the master must take appropriate
action.
The PEC byte is automatically inserted in a slave transmitter transmission if PEC enabled
when NBYTES reaches zero. The PEC byte is identified in a slave receiver transmission if
PEC enabled when NBYTES reaches zero. NBYTES must therefore be set to the total number
of data bytes in the transmission, including the PEC byte.
The Timing Register (TR) configures the SMBus timeout values. If a timeout occurs, the slave
will leave the bus. The SR.SMBTOUT bit is also set.
A slave can get the master’s attention by pulling the SMBALERT line low. This is done by set-
ting the CR.SMBAL bit. This will also enable address match on the Alert Response Address
(ARA).
The TWIS is able to wake the device up from sleep modes upon an address match, including
modes where CLK_TWIS is stopped. If a TWI Start condition is received in a sleep mode
where CLK_TWIS is stopped, TWIS will stretch TWCK until CLK_TWIS has started. The time
required for restarting CLK_TWIS depends on which sleep mode the system was in.
When CLK_TWIS has been restarted, the TWCK stretching is released and the slave address
will be received on the TWI bus. To save power, only a limited part of the device including
TWIS receives a clock at this time. If the address phase causes a TWIS address match, the
entire device will be wakened and normal TWIS address match actions performed. Normal
TWI transfer will then follow. If the TWIS was not addressed by the transfer, CLK_TWIS will
automatically be stopped and the system will go back to the original sleep mode.
This chapter lists the different bus events, and how these affects bits in the TWIS registers.
This is intended to help writing drivers for the TWIS.
Table 23-5.
Event
Slave transmitter has sent a
data byte
Slave receiver has received
a data byte
Start+Sadr on bus, but
address is to another slave
Start+Sadr on bus, current
slave is addressed, but
address match enable bit in
CR is not set
Bus Events
Effect
SR.THR is cleared.
SR.BTF is set.
The value of the ACK bit sent immediately after the data byte is given
by CR.ACK.
SR.RHR is set.
SR.BTF is set.
SR.NAK updated according to value of ACK bit received from master.
None.
None.
AT32UC3L
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