AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 124

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

10.7.17
Name:
Access Type:
Offset:
Reset Value:
• MON1CH: Performance Monitor Channel 1
• MON0CH: Performance Monitor Channel 0
• CH1RES: Performance Channel 1 Counter Reset
• CH0RES: Performance Channel 0 Counter Reset
• CH1OF: Performance Channel 1 Overflow Freeze
• CH1OF: Performance Channel 0 Overflow Freeze
• CH1EN: Performance Channel 1 Enable
• CH0EN: Performance Channel 0 Enable
32099A–AVR32–06/09
31
23
15
7
-
-
-
-
The PDCA channel number to monitor with counter n
Due to performance monitor hardware resource sharing, the two performance monitor channels should NOT be programmed to
monitor the same PDCA channel. This may result in UNDEFINED monitor behavior.
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the counter in performance channel 1.
This bit always reads as zero.
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the counter in performance channel 0.
This bit always reads as zero.
0: The performance channel registers are reset if DATA or STALL overflows.
1: All performance channel registers are frozen just before DATA or STALL overflows.
0: The performance channel registers are reset if DATA or STALL overflows.
1: All performance channel registers are frozen just before DATA or STALL overflows.
0: Performance channel 1 is disabled.
1: Performance channel 1 is enabled.
0: Performance channel 0 is disabled.
1: Performance channel 0 is enabled.
Performance Control Register
30
22
14
6
-
-
-
-
PCONTROL
Read/Write
0x800
0x00000000
CH1OF
29
21
13
5
-
CH0OF
28
20
12
4
-
27
19
11
3
-
-
MON1CH
MON0CH
26
18
10
2
-
-
CH1RES
CH1EN
25
17
9
1
AT32UC3L
CH0RES
CH0EN
24
16
8
0
124