AT32UC3L064_1 ATMEL [ATMEL Corporation], AT32UC3L064_1 Datasheet - Page 281

• Manufacturer Part Number: AT32UC3L064_1
• Description: AVR32 32-bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

16.4.1
16.4.2
16.4.3
16.4.4
16.5
16.5.1
16.5.1.1
16.5.1.2
32099A–AVR32–06/09
Functional Description
Power Management
Clocks
Debug Operation
Fuses
Basic Mode
WDT Control Register Access
Changing CLK_CNT Clock Source
When the WDT is enabled, the WDT remains clocked in all sleep modes. It is not possible to
enter sleep modes where the source clock of CLK_CNT is stopped. Attempting to do so will
result in the chip entering the lowest sleep mode where the source clock is running, leaving the
WDT operational. Please refer to the Power Manager chapter for details about sleep modes.
After a watchdog reset the WDT bit in the Reset Cause Register (RCAUSE) in the Power Man-
ager will be set.
The clock for the WDT bus interface (CLK_WDT) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the WDT before disabling the clock, to avoid freezing the WDT in an undefined state.
There are two possible clock sources for the Watchdog Timer (CLK_CNT):
The WDT counter is frozen during debug operation, unless the Run In Debug bit in the Develop-
ment Control Register is set and the bit corresponding to the WDT is set in the Peripheral Debug
Register. Please refer to the On-Chip Debug chapter in the AVR32UC Technical Reference
Manual for details. If the WDT counter is not frozen during debug operation it will need periodi-
cally clearing to avoid a watchdog reset.
The WDT can be enabled at reset. This is controlled by the WDTAUTO fuse, see
for details. Please refer to the Fuse Settings section in the Flash Controller chapter for details
about WDTAUTO and how to program the fuses.
To avoid accidental disabling of the watchdog, the Control Register (CTRL) must be written
twice, first with the KEY field set to 0x55, then 0xAA without changing the other bits. Failure to
do so will cause the write operation to be ignored, and the value in the CTRL Register will not be
changed.
After any reset, except for watchdog reset, CLK_CNT will be enabled with the RCSYS as
source.
• System RC oscillator (RCSYS): This oscillator is always enabled when selected as clock
• 32 KHz crystal oscillator (OSC32K): This oscillator has to be enabled in the System Control
source for the WDT. Please refer to the Power Manager chapter for details about the RCSYS
and sleep modes. Please refer to the Electrical Characteristics chapter for the characteristic
frequency of this oscillator.
Interface before using it as clock source for the WDT. The WDT will not be able to detect if
this clock is stopped.
AT32UC3L
Section 16.5.4
281