r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 966

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
Legend:
S:
SLA:
R/W:
A:
DATA: Transferred data
P:
16.4.2
In I
data, and the slave device returns an acknowledge signal. The transmission procedure and
operations in master transmit mode are described below.
1. Set the ICE bit in ICCRA to 1. Set the WAIT bit in ICMR and the CKS3 to CKS0 bits in
2. Read the BBSY flag in ICCRB to confirm that the bus is free. Set the MST and TRS bits in
3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data
4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1
5. The transmit data after the second byte is written to ICDRT every time TDRE is set, thus
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
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ICCR1 to 1. (Initial setting)
ICCRA to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV
instruction. (Start condition issued) This generates the start condition.
show the slave address and R/W) to ICDRT. After this, when TDRE is cleared to 0, data is
transferred from ICDRT to ICDRS. TDRE is set again.
at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the
slave device has been selected. Then, write second byte data to ICDRT, and clear TDRE and
TEND. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop
condition. To issue the stop condition, write 0 to BBSY and SCP using MOV instruction. SCL
is fixed low until the transmit data is prepared or the stop condition is issued.
clearing TDRE.
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
C bus format master transmit mode, the master device outputs the transmit clock and transmit
Start condition. The master device drives SDA from high to low while SCL is high.
Slave address
Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
Acknowledge. The receiving device drives SDA to low.
Stop condition. The master device drives SDA from low to high while SCL is high.
Master Transmit Operation
2
C Bus Interface 2 (IIC2)