r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 244

no-image

r4f2426

Manufacturer Part Number
r4f2426
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
r4f24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
r4f24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
r4f24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
r4f24268NVRFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
r4f24268NVZFQV
Manufacturer:
REA
Quantity:
150
Part Number:
r4f24268NVZFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
r4f24269NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
r4f24269NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Bus Controller (BSC)
6.7
In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing
performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM
space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst
operation is also possible, using fast page mode.
6.7.1
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The
relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.5.
Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2
to 5), and continuous area (areas 2 to 5).
Table 6.5
Note:
With continuous DRAM space, RAS2 is valid. The bus specifications (bus width, number of wait
states, etc.) for continuous DRAM space conform to the settings for area 2.
6.7.2
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table
6.6 shows the relation between the settings of MXC2 to MXC0 and the shift size.
The MXC2 bit should be cleared to 0 when the DRAM interface is used.
Rev. 1.00 Sep. 19, 2008 Page 216 of 1270
REJ09B0466-0100
RMTS2
0
1
*
DRAM Interface
Setting DRAM Space
Address Multiplexing
Reserved (setting prohibited) in the H8S/2426 Group and H8S/2424 Group.
RMTS1
0
1
0
1
Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space
RMTS0
1
0
1
0
1
0
1
Area 5
Normal space
Normal space
DRAM space
Continuous synchronous DRAM space*
Mode register settings of synchronous DRAM*
Reserved (setting prohibited)
Continuous
DRAM space
Area 4
Normal space
Normal space
DRAM space
Continuous
DRAM space
Area 3
Normal space
DRAM space
DRAM space
Continuous
DRAM space
Area 2
DRAM space
DRAM space
DRAM space
Continuous
DRAM space

Related parts for r4f2426